公开(公告)号：US5561429A

公开(公告)日：1996-10-01

申请号：US852877

申请日：1986-04-16

申请人： M. Halberstam ,  James E. Meister ,  Moshe Mazin ,  Dennis A. Henlin ,  Jun-ichi Sano ,  Edward T. Lewis

发明人： M. Halberstam ,  James E. Meister ,  Moshe Mazin ,  Dennis A. Henlin ,  Jun-ichi Sano ,  Edward T. Lewis

IPC分类号： G06F17/30 ,  G11C15/00 ,  G06F7/02

CPC分类号： G06F17/30982 ,  G11C15/00

摘要： A content limit addressable memory (CLAM) having a plurality of lower and upper limits stored therein for comparison to corresponding subfields of an input word. Each corresponding upper and lower limit forms a bracket. Corresponding brackets form a window. The brackets correspond to the subfields and are of the same number of bits. The brackets and subfields are alterable in width to allow each bracket and subfield to have any number of bits in multiples of two. A valid match of the input word with any window can occur with any combination of the brackets of a window matching or not matching the corresponding subfields of the input word. A plurality of outputs corresponding to each of the windows indicates a match of the corresponding window to the input word. Additionally, the CLAM can compare data stored therein against an applied window with the matching operations as described above.

摘要翻译： 存储有多个下限和上限的内容限制可寻址存储器（CLAM），用于与输入字的相应子字段进行比较。 每个对应的上限和下限形成一个支架。 相应的括号形成一个窗口。 括号对应于子字段并且具有相同的位数。 括号和子字段的宽度是可变的，以允许每个括号和子字段具有任意数量的二进制数。 输入字与任何窗口的有效匹配可以与匹配或不匹配输入字的相应子字段的窗口的括号的任意组合发生。 对应于每个窗口的多个输出表示对应的窗口与输入单词的匹配。 此外，CLAM可以将如上所述的匹配操作来比较存储在其中的数据与应用的窗口。

公开(公告)号：US4901285A

公开(公告)日：1990-02-13

申请号：US316590

申请日：1989-02-27

申请人： Jun-ichi Sano ,  Moshe Mazin ,  Lance A. Glasser

发明人： Jun-ichi Sano ,  Moshe Mazin ,  Lance A. Glasser

IPC分类号： G11C17/12

CPC分类号： G11C17/126

摘要： An integrated circuit memory having a plurality of row lines; a plurality of select lines; a plurality of output lines; a plurality of memory cells; each pair of memory cells having common outputs coupled to a select one of the plurality of output lines and common address inputs coupled to a select one of the plurality of row lines, wherein ambiguity of which memory cell of the pair of memory cells to be selected, being coupled to a select one of the plurality of row lines and a select one of the plurality of output lines, is determined by two selected ones of the plurality of select lines coupled thereto. Also provided is a first decoder, responsive to an input address, for enabling a select one of the plurality of row lines, and a second decoder, responsive to the row lines and to the input address, for enabling a select one of the select lines which corresponds to pairs of memory cells with an enabled row line.

摘要翻译： 一种具有多条行线的集成电路存储器; 多条选择线; 多个输出线; 多个存储单元; 每对存储器单元具有耦合到所述多条输出线中的选择一条输出线的公共输出和耦合到所述多条行线中的选择一条线的公共地址输入，其中所选择的所述一对存储器单元中的存储单元的模糊性 耦合到所述多行输入行中的选择一行和所述多条输出行中的选择一行由所耦合的所述多条选择行中的两个选定行选择。 还提供了响应于输入地址以启用多条行线中的选择行的第一解码器，以及响应于行线和输入地址的第二解码器，用于启用选择线中的选择线 其对应于具有启用行行的存储器单元对。

公开(公告)号：US4845668A

公开(公告)日：1989-07-04

申请号：US131474

申请日：1987-12-10

申请人： Jun-ichi Sano ,  Edward T. Lewis

发明人： Jun-ichi Sano ,  Edward T. Lewis

IPC分类号： G11C15/00 ,  G11C15/04

CPC分类号： G11C15/04

摘要： A variable field content addressable memory (VFCAM) unit cell comprises a 4-bit content addressable memory, a programmer and a field selector. A limited capability of comparing between limits is provided by using mask bits at the data line inputs to the VFCAM unit cell. A plurality of VFCAM unit cells may be cascaded vertically and horizontally to provide a Y words by X bits VFCAM array. The VFCAM array is programmable by a field code coupled to field partition logic which selects the same number of fields in all memory locations and the number of bits in each field, and an operational VFCAM system results when the VFCAM array is coupled to an input address decoder, an I/O register and an output encoder.

摘要翻译： 可变字段内容可寻址存储器（VFCAM）单元单元包括4位内容可寻址存储器，编程器和字段选择器。 通过在VFCAM单元的数据线输入端使用掩码位来提供限制之间的比较限制的能力。 多个VFCAM单元可以垂直和水平级联，以通过X位VFCAM阵列提供Y个字。 VFCAM阵列可以通过耦合到场分区逻辑的字段代码来编程，该字段代码在所有存储器位置中选择相同数量的字段，并且在每个字段中选择位数，并且当VFCAM阵列耦合到输入地址时产生操作VFCAM系统 解码器，I / O寄存器和输出编码器。

公开(公告)号：US4321661A

公开(公告)日：1982-03-23

申请号：US219472

申请日：1980-12-23

申请人： Jun-ichi Sano

发明人： Jun-ichi Sano

IPC分类号： H02M3/07 ,  H02M3/18

CPC分类号： H02M3/07

摘要： An NMOS FET circuit for charging a storage capacitor to a voltage higher than the power supply voltage. The circuit includes several stages each including a capacitance and FET switches. In response to a high level control signal the FET's in effect connect each capacitance between the supply voltage and ground to charge the capacitances. Then, in response to a low level control signal the FET's in effect connect the capacitances in series between the supply voltage and the storage capacitor thus transferring a portion of the charges in the capacitances into the storage capacitor. The charge placed in the storage capacitor produces a voltage thereacross which is greater than the supply voltage.

摘要翻译： 一种用于将存储电容器充电到高于电源电压的电压的NMOS FET电路。 电路包括几个阶段，每个阶段包括电容和FET开关。 响应于高电平控制信号，FET实际上连接电源电压和地之间的每个电容以对电容充电。 然后，响应于低电平控制信号，FET实际上将电容串联在电源电压和存储电容器之间，从而将电容中的一部分电荷转移到存储电容器中。 放置在存储电容器中的电荷产生大于电源电压的电压。

公开(公告)号：US4307308A

公开(公告)日：1981-12-22

申请号：US95765

申请日：1979-11-19

申请人： Jun-ichi Sano

发明人： Jun-ichi Sano

IPC分类号： H03K19/0185 ,  H03L5/00

CPC分类号： H03K19/018507

摘要： Circuit for converting input signals at TTL voltage levels to output signals at voltage levels for use with MOS logic circuits. The circuit employs an arrangement of NMOS FET's. Six FET's are arranged in pairs to form three inverters. Another FET is connected in series between the input terminal and different portions of the first and second of the three inverters. The output of the second inverter is fed back to the gate electrode of one of the FET's of the first inverter and to the gate electrode of the series connected FET. The output of the second inverter is also applied to the third inverter. The excursion between voltage levels representing logic 1 and logic 0 at the output of the third inverter is greater than the excursion between voltage levels representing logic 1 and logic 0 at the input to the circuit.

摘要翻译： 用于将TTL电压电平的输入信号转换为用于MOS逻辑电路的电压电平的电路。 该电路采用NMOS FET的布置。 成对配置六个FET，形成三个逆变器。 另一个FET串联连接在输入端和三个逆变器中的第一和第二反相器的不同部分之间。 第二反相器的输出反馈到第一反相器的FET之一的栅极电极和串联连接的FET的栅电极。 第二反相器的输出也施加到第三反相器。 在第三反相器的输出处表示逻辑1和逻辑0的电压电平之间的偏移大于在电路的输入处表示逻辑1和逻辑0的电压电平之间的偏移。

公开(公告)号：US5884154A

公开(公告)日：1999-03-16

申请号：US672486

申请日：1996-06-26

申请人： Jun-ichi Sano ,  Raymond S. Pengelly ,  Miles E. Goff

发明人： Jun-ichi Sano ,  Raymond S. Pengelly ,  Miles E. Goff

IPC分类号： H03D7/14 ,  H03F3/45 ,  H04B1/28 ,  H04B1/16

CPC分类号： H03F3/45188 ,  H03D7/1433 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0025 ,  H03D2200/0084

摘要： A mixer circuit is provided which incorporates inductive elements for low voltage applications. The circuit consists of a balanced amplifier and a switch composed of transistor pairs driven by a local oscillator signal for multiplying the signal to produce a circuit output signal having a predetermined intermediate frequency. Inductors are used to provide degenerative feedback in the balanced amplifier portion of the circuit. The inductors generate negligible noise and produce a negligible dc voltage drop. The transistors in the circuit are thereby maintained in saturation regions of operation as desired. In accordance with another aspect of the invention, an inductor or, alternatively, a parallel inductor-capacitor circuit, is used as a constant current source in conjunction with the input transistors in the balanced amplifier portion of the circuit.

摘要翻译： 提供了一种混合电路，其中包含用于低电压应用的电感元件。 电路由平衡放大器和由本机振荡器信号驱动的晶体管组构成的开关构成，用于对信号进行乘法，以产生具有预定中间频率的电路输出信号。 电感器用于在电路的平衡放大器部分中提供退化反馈。 电感器产生可忽略的噪声并产生可忽略的直流电压降。 因此，电路中的晶体管因此被保持在饱和的操作区域中。 根据本发明的另一方面，电感器或可替代地，并联电感器 - 电容器电路被用作与电路的平衡放大器部分中的输入晶体管一起的恒流源。

公开(公告)号：US4340867A

公开(公告)日：1982-07-20

申请号：US204092

申请日：1980-11-05

申请人： Jun-ichi Sano

发明人： Jun-ichi Sano

IPC分类号： H03F1/30 ,  H03F3/16

CPC分类号： H03F1/301 ,  H03F3/16

摘要： An inverter amplifier employing NMOS FET's having a plurality of capacitance coupled inverter amplifier stages arranged in series. A DC bias is provided at the input of each amplifier stage by a DC bias generator of a reference voltage source, an operational amplifier, and a reference inverter arranged in a negative feedback loop. The DC bias generator is applied to the input of each amplifier stage.

摘要翻译： 一种采用具有串联布置的多个电容耦合的反相放大器级的NMOS FET的反相放大器。 通过参考电压源的DC偏置发生器，运算放大器和布置在负反馈回路中的参考反相器，在每个放大器级的输入处提供DC偏置。 DC偏置发生器应用于每个放大器级的输入。