公开(公告)号：US20210119645A1

公开(公告)日：2021-04-22

申请号：US16658191

申请日：2019-10-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Huai SHIH ,  Yu-Ming HUANG ,  Hsiang-Pang LI ,  Hsi-Chia CHANG

IPC: H03M13/25 ,  H03M13/11 ,  H03M13/29 ,  H03M13/15

Abstract: The present invention discloses an encoder, a decoder, an encoding method and a decoding method based on Low-Density Parity-Check (LDPC) code. The encoding method comprises: receiving, by an encoder, an information for encoding; generating, by the encoder, a first portion codeword according to a first encoding rule and the information for encoding, wherein the first encoding rule is an encoding rule configured to generate LDPC code; generating, by the encoder, a second portion codeword according to a second encoding rule different from the first encoding rule and a double check region of the first portion codeword; and concatenating, by the encoder, the first portion codeword and the second portion codeword to generate a codeword. A plurality of trapping sets corresponding to the first encoding rule include at least one error bit within the double check region.

公开(公告)号：US20250158628A1

公开(公告)日：2025-05-15

申请号：US18736681

申请日：2024-06-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Han-Wen HU ,  Yung-Chun LI ,  Chih-Chang HSIEH ,  BO-RONG LIN ,  Huai-Mu WANG ,  Chih-Huai SHIH

IPC: H03M1/12 ,  H03M1/38 ,  H03M1/50

Abstract: An analog-to-digital conversion device, includes the following elements. A sensing circuit, coupled to a bit line of a memory array, and used to sense a current in the bit line to generate a bit-sequence, the bit-sequence has a form of a thermometer code to represent an analog value. A latch logic circuit, including a plurality of latches and a plurality of logic circuits to form a page buffer of the memory array, and used to generate a bit-set according to the bit-sequence, the bit-set has a form of a binary code to represent a digital value. The latches and the logic circuits are used to perform a conversion process to convert the bit-sequence into the bit-set, and the conversion process has a bit width.

公开(公告)号：US20250156420A1

公开(公告)日：2025-05-15

申请号：US18655472

申请日：2024-05-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Huai SHIH ,  Han-Wen HU ,  Huai-Mu WANG ,  Yung-Chun LI

IPC: G06F16/2455 ,  G06F16/28

Abstract: A filtered search method, for performing a search within a data set, and the data set includes several data points. The filtered search method includes the following steps. Dividing the data set into several clusters based on a similarity of the data points. Dividing each of the clusters into an inlier part and an outlier part based on a distribution density of the data points. Performing a coarse search on all of the inlier parts, to filter out inlier parts of a first candidate number. Performing a fine search on the inlier parts of the first candidate number, to search data points of a second candidate number. Obtaining a search result based on the data points of the second candidate number, and the data points of the second candidate number are close to a target point.

公开(公告)号：US20190245653A1

公开(公告)日：2019-08-08

申请号：US15890500

申请日：2018-02-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Ming HUANG ,  Chih-Huai SHIH ,  Hsiang-Pang LI ,  Hsi-Chia CHANG

IPC: H04L1/00 ,  H03M13/13 ,  H03M13/00

CPC classification number: H04L1/0058 ,  H03M13/13 ,  H03M13/616

Abstract: A method for generating a polar code includes the steps of: establishing a plurality of polarization matrices that receive a plurality of first input bits via a plurality of first input channels and provide a plurality of first output bits on a plurality of first output channels; selecting at least one to-be-enhanced input channel from the first input channels of the polarization matrices; providing a re-polarization matrix that receives a plurality of second input bits via a plurality of second input channels and provides a plurality of second output bits on a plurality of second output channels, wherein a part of the second output bits is used as the first output bit(s) on the at least one to-be-enhanced input channel; and providing a polar code that comprises the first output bits and a remaining part of the second output bits.