公开(公告)号：US20190198098A1

公开(公告)日：2019-06-27

申请号：US15850280

申请日：2017-12-21

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shang-Chi YANG ,  Chun-Yu LIAO ,  Ken-Hui CHEN

IPC: G11C13/00

Abstract: A memory device including an array of memory cells including bit lines, and biasing circuitry cells. A sense amplifier has a data line input connected to a data line, and a reference input. The controllable reference current source can be connected to the reference input of the sense amplifier. Control circuits on the device are configured to cause execution of a read operation, where the read operation includes a first phase in which the array is biased to induce leakage current on the selected bit line, and a second phase in which the array is biased to read a selected memory cell on the selected bit line. A circuit on the device is configured to sample the leakage current in the first phase, and to control the controllable reference current source during the second phase, as a function of the sampled leakage current.

公开(公告)号：US20180342302A1

公开(公告)日：2018-11-29

申请号：US15841622

申请日：2017-12-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Kuen-Long CHANG ,  Ken-Hui CHEN ,  Su-Chueh LO ,  Chun-Yu LIAO

IPC: G11C16/26 ,  G11C16/04 ,  G11C7/06 ,  G11C7/10 ,  G11C11/4093 ,  G06F13/40 ,  G06F12/02

Abstract: The embodiment of the present invention discloses a memory device and a method for operating the same. The memory device includes a memory array and a logic circuit. The logic circuit is coupled to the memory array, and is configured to perform a corresponding operation in response to an operation command from a controller. When an interruption event occurs during the corresponding operation, the logic circuit records a memory status, and the logic circuit further is configured to output the memory status to the controller in response to a status read command from the controller.

公开(公告)号：US20190188131A1

公开(公告)日：2019-06-20

申请号：US15841640

申请日：2017-12-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Su-Chueh LO ,  Chun-Yu LIAO

IPC: G06F12/06 ,  G11C11/417 ,  G11C11/16

CPC classification number: G06F12/0646 ,  G06F2003/0691 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/417

Abstract: Provided is a memory device including: a memory array, including a flag memory array having a plurality of flag memory cells and a data memory array having a plurality of data memory cells, the corresponding flag memory cells being used to record whether the corresponding data memory cells have been written or not. In initialization, the flag memory array is initialized by the control circuit but the data memory array is not initialized.