公开(公告)号：US20150380430A1

公开(公告)日：2015-12-31

申请号：US14554759

申请日：2014-11-26

Applicant: Macronix International Co., Ltd.

Inventor： Sheng-Chih Lai

IPC: H01L27/115 ,  H01L21/265 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/7827

Abstract: A method is provided for manufacturing a memory device. A plurality of layers of a first semiconductor material is formed, and a plurality of holes is formed through the layers. An etch process is applied to the layers through the holes, to form pull-back regions in the layers adjacent and surrounding the holes. A film of second semiconductor material is deposited over the holes and into the pull-back regions. Portions of the film are removed from the holes while leaving elements of the second semiconductor material in the pull-back regions in contact with the first semiconductor material. The holes are filled with insulating material. Layers in the plurality of layers have respective first doping concentration profiles, and the elements of the second semiconductor material in the pull-back regions have second doping concentration profiles. The second doping concentration profiles establish a higher conductivity in the elements of second semiconductor material.

Abstract translation: 提供了一种用于制造存储器件的方法。 形成多层第一半导体材料，并且通过层形成多个孔。 通过孔将蚀刻工艺施加到层上，以在邻近和围绕孔的层中形成拉回区域。 第二半导体材料的膜沉积在孔上并进入拉回区域。 在与第一半导体材料接触的拉回区域中留下第二半导体材料的元件的同时从孔中移除部分的膜。 孔中填充绝缘材料。 多个层中的层具有各自的第一掺杂浓度分布，并且在拉回区中的第二半导体材料的元素具有第二掺杂浓度分布。 第二掺杂浓度分布在第二半导体材料的元件中建立更高的导电性。

公开(公告)号：US20160197041A1

公开(公告)日：2016-07-07

申请号：US14589006

申请日：2015-01-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Sheng-Chih Lai ,  Wei-Chen Chen

IPC: H01L23/535 ,  H01L23/528 ,  H01L21/28 ,  H01L21/768 ,  H01L21/3213 ,  H01L27/115 ,  H01L23/532

CPC classification number: H01L21/28282 ,  H01L27/11565 ,  H01L27/11582

Abstract: A memory device comprises a first conductive stripe, a first memory layer, a first conductive pillar, a first dielectric layer and a first conductive plug. The first conductive strip extends along a first direction. The first memory layer extends along a second direction adjacent to and overlapping with the first conductive stripe to define a first memory area thereon. The first conductive pillar extends along the second direction and overlapping with the first memory area. The first dielectric layer extends along the second direction adjacent to the first conductive stripe, the first memory layer and the first conductive pillar. The first conductive plus extends along the second direction and at least overlaps with a portion of the first conductive stripe, wherein the first conductive plus is electrically insulated from the first conductive stripe, the first memory layer and the first conductive pillar by the first dielectric layer.

Abstract translation: 存储器件包括第一导电条，第一存储层，第一导电柱，第一介电层和第一导电插塞。 第一导电条沿着第一方向延伸。 第一存储层沿着与第一导电条相邻并与其重叠的第二方向延伸以在其上限定第一存储区。 第一导电柱沿着第二方向延伸并与第一存储区重叠。 第一电介质层沿着与第一导电条，第一存储层和第一导电柱相邻的第二方向延伸。 第一导电加极沿着第二方向延伸并且至少与第一导电条的一部分重叠，其中第一导电加上与第一导电条电绝缘，第一存储层和第一导电柱由第一介电层 。

公开(公告)号：US09356040B2

公开(公告)日：2016-05-31

申请号：US14554759

申请日：2014-11-26

Applicant: Macronix International Co., Ltd.

Inventor： Sheng-Chih Lai

IPC: H01L29/76 ,  H01L21/336 ,  H01L27/115 ,  H01L21/306 ,  H01L21/265 ,  H01L21/02

CPC classification number: H01L27/11582 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/7827

Abstract: A method is provided for manufacturing a memory device. A plurality of layers of a first semiconductor material is formed, and a plurality of holes is formed through the layers. An etch process is applied to the layers through the holes, to form pull-back regions in the layers adjacent and surrounding the holes. A film of second semiconductor material is deposited over the holes and into the pull-back regions. Portions of the film are removed from the holes while leaving elements of the second semiconductor material in the pull-back regions in contact with the first semiconductor material. The holes are filled with insulating material. Layers in the plurality of layers have respective first doping concentration profiles, and the elements of the second semiconductor material in the pull-back regions have second doping concentration profiles. The second doping concentration profiles establish a higher conductivity in the elements of second semiconductor material.

Abstract translation: 提供了一种用于制造存储器件的方法。 形成多层第一半导体材料，并且通过层形成多个孔。 通过孔将蚀刻工艺施加到层上，以在邻近和围绕孔的层中形成拉回区域。 第二半导体材料的膜沉积在孔上并进入拉回区域。 在与第一半导体材料接触的拉回区域中留下第二半导体材料的元件的同时从孔中移除部分的膜。 孔中填充绝缘材料。 多个层中的层具有各自的第一掺杂浓度分布，并且在拉回区中的第二半导体材料的元素具有第二掺杂浓度分布。 第二掺杂浓度分布在第二半导体材料的元件中建立更高的导电性。

公开(公告)号：US09419010B2

公开(公告)日：2016-08-16

申请号：US14488937

申请日：2014-09-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yen-Hao Shih ,  Chih-Ping Chen ,  Sheng-Chih Lai

IPC: H01L27/115 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/768 ,  H01L27/11556

Abstract: A plurality of semiconductor layers is etched to define a first plurality of stacks of active strips between a first plurality of trenches. A first memory layer is formed on side surfaces of active strips in the first plurality of trenches, and a first layer of conductive material is formed over the first memory layer. The first plurality of stacks is etched to define a second plurality of stacks of active strips between a second plurality of trenches of the plurality of semiconductor layers. A second memory layer is formed on side surfaces of active strips in the second plurality of trenches, and a second layer of conductive material is formed over the second memory layer. Channel regions of memory cells in the memory device are formed in active strips of the plurality of semiconductor layers in the second plurality of stacks.

Abstract translation: 蚀刻多个半导体层以在第一多个沟槽之间限定活动条的第一多个堆叠。 第一存储层形成在第一多个沟槽中的活性条的侧表面上，并且第一层导电材料形成在第一存储层上。 蚀刻第一组多个叠层以在多个半导体层的第二多个沟槽之间限定有效条带的第二多个叠层。 第二存储层形成在第二多个沟槽中的活性条的侧表面上，并且第二层导电材料形成在第二存储层上。 存储器件中的存储器单元的通道区域形成在第二多个堆叠中的多个半导体层的有源条带中。