公开(公告)号：US20220122677A1

公开(公告)日：2022-04-21

申请号：US17566080

申请日：2021-12-30

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Chun Liu

IPC: G11C16/34 ,  G06F11/10 ,  G06F3/06 ,  G11C29/00 ,  G11C11/56 ,  G11C16/16 ,  G11C16/08 ,  G11C16/24 ,  G11C29/42

Abstract: A memory device includes a memory cell array and a memory controller. The memory cell array includes a plurality of memory blocks. Each of the memory blocks includes a plurality of word lines. A plurality of memory chunks is coupled to at least one of the word lines. The memory controller is configured to program data to a particular memory chunk of the plurality of memory chunks by performing a chunk operation that includes selecting a particular word line from the plurality of word lines, selecting a particular memory chunk from the plurality of memory chunks that are coupled to the particular word line, and applying a program voltage to a particular memory block corresponding to the particular memory chunk to program data to the particular memory chunk.

公开(公告)号：US10387243B2

公开(公告)日：2019-08-20

申请号：US15835859

申请日：2017-12-08

Applicant: Macronix International Co., Ltd.

Inventor： Ting-Yu Liu ,  Yi-Chun Liu

IPC: G06F12/00 ,  G06F11/10 ,  G06F3/06 ,  G06F12/02

Abstract: Systems, methods, and apparatus including computer-readable mediums for managing data arrangement in a super block in a memory such as NAND flash memory are provided. In one aspect, a memory controller includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to determine one or more characteristics of data to be written, allocate a super page of a super block based on the determined characteristics of the data and block information of the physical blocks of the planes, the super block combining one or more physical blocks from the planes, the super page combining one or more single pages from the corresponding one or more physical blocks in the super block, arrange the data to the one or more single pages in the super page, and program the super page to write the data in the one or more single pages.

公开(公告)号：US20180165198A1

公开(公告)日：2018-06-14

申请号：US15378508

申请日：2016-12-14

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Chun Liu

IPC: G06F12/0815 ,  G06F12/0891

CPC classification number: G06F12/0815 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0891 ,  G06F2212/466 ,  G06F2212/60 ,  G06F2212/621 ,  G06F2212/7201 ,  G06F2212/7207

Abstract: A request is received to access physical information of a memory unit included in a memory device. A determination is made whether the physical information is available in a physical information table present in a memory cache. If the physical information of the memory unit is available in the table, the physical information is accessed from the table. If the physical information is not available in the table, a global directory in the memory cache is accessed, which indicates locations in a non-volatile memory that store the total number of the physical information blocks. From the global directory, a particular location in the non-volatile memory storing a particular physical information block that includes the physical information of the memory unit is determined. The particular physical information block is loaded into the table and the physical information of the memory unit is accessed from the particular physical information block.

公开(公告)号：US11645006B2

公开(公告)日：2023-05-09

申请号：US16863202

申请日：2020-04-30

Applicant: Macronix International Co., Ltd.

Inventor： Ting-Yu Liu ,  Yi-Chun Liu

IPC: G06F3/06 ,  G06F12/123 ,  G06F12/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0674 ,  G06F12/10 ,  G06F12/124

Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

公开(公告)号：US11257552B2

公开(公告)日：2022-02-22

申请号：US16281258

申请日：2019-02-21

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Chun Liu

IPC: G11C16/34 ,  G06F3/06 ,  G06F11/10 ,  G11C29/00 ,  G11C11/56 ,  G11C16/16 ,  G11C16/08 ,  G11C16/24 ,  G11C29/42

Abstract: A memory device includes a memory cell array and a memory controller. The memory cell array includes a plurality of memory blocks. Each of the memory blocks includes a plurality of word lines. A plurality of memory chunks is coupled to at least one of the word lines. The memory controller is configured to program data to a particular memory chunk of the plurality of memory chunks by performing a chunk operation that includes selecting a particular word line from the plurality of word lines, selecting a particular memory chunk from the plurality of memory chunks that are coupled to the particular word line, and applying a program voltage to a particular memory block corresponding to the particular memory chunk to program data to the particular memory chunk.

公开(公告)号：US20210397510A1

公开(公告)日：2021-12-23

申请号：US16906712

申请日：2020-06-19

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Chun Liu ,  Wei Jie Chen ,  Ching Ting Lu ,  Zheng Wu

IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G06F12/0882 ,  G11C16/34 ,  G11C16/14 ,  G11C16/08

Abstract: Systems, methods, and apparatus including computer-readable mediums for managing open blocks in memory systems such as NAND flash memory devices are provided. In one aspect, a memory system includes a memory and a memory controller. The memory includes multiple blocks each having a plurality of word lines. The memory controller is coupled to the memory and configured to: evaluate a read disturbance level of an open block, the open block having one or more programmed word lines and one or more blank word lines, and in response to determining that the read disturbance level of the open block is beyond a threshold level, manage each memory cell in at least one of the blank word lines to have a smaller data storing capacity than each memory cell in at least one of the one or more programmed word lines so as to reduce impact of read disturbance.

公开(公告)号：US20190272231A1

公开(公告)日：2019-09-05

申请号：US16418428

申请日：2019-05-21

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Chun Liu

IPC: G06F12/0817 ,  G06F12/0868 ,  G06F12/02 ,  G06F12/0895

Abstract: A request is received to access physical information of a memory unit included in a memory device. A determination is made whether the physical information is available in a physical information table present in a memory cache. If the physical information of the memory unit is available in the table, the physical information is accessed from the table. If the physical information is not available in the table, a global directory in the memory cache is accessed, which indicates locations in a non-volatile memory that store the total number of the physical information blocks. From the global directory, a particular location in the non-volatile memory storing a particular physical information block that includes the physical information of the memory unit is determined. The particular physical information block is loaded into the table and the physical information of the memory unit is accessed from the particular physical information block.

公开(公告)号：US10318423B2

公开(公告)日：2019-06-11

申请号：US15378508

申请日：2016-12-14

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Chun Liu

IPC: G06F12/0815 ,  G06F12/0817 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/1009

Abstract: A request is received to access physical information of a memory unit included in a memory device. A determination is made whether the physical information is available in a physical information table present in a memory cache. If the physical information of the memory unit is available in the table, the physical information is accessed from the table. If the physical information is not available in the table, a global directory in the memory cache is accessed, which indicates locations in a non-volatile memory that store the total number of the physical information blocks. From the global directory, a particular location in the non-volatile memory storing a particular physical information block that includes the physical information of the memory unit is determined. The particular physical information block is loaded into the table and the physical information of the memory unit is accessed from the particular physical information block.

公开(公告)号：US12086467B2

公开(公告)日：2024-09-10

申请号：US18175726

申请日：2023-02-28

Applicant: Macronix International Co., Ltd.

Inventor： Ting-Yu Liu ,  Yi-Chun Liu

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/123

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0674 ,  G06F12/10 ,  G06F12/124

Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

公开(公告)号：US11340980B2

公开(公告)日：2022-05-24

申请号：US16906712

申请日：2020-06-19

Applicant: Macronix International Co., Ltd.

Inventor： Yi-Chun Liu ,  Wei Jie Chen ,  Ching Ting Lu ,  Zheng Wu

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/07 ,  G06F11/30 ,  G11C16/08 ,  G06F12/0882 ,  G11C16/34 ,  G11C16/14 ,  G06F12/02

Abstract: Systems, methods, and apparatus including computer-readable mediums for managing open blocks in memory systems such as NAND flash memory devices are provided. In one aspect, a memory system includes a memory and a memory controller. The memory includes multiple blocks each having a plurality of word lines. The memory controller is coupled to the memory and configured to: evaluate a read disturbance level of an open block, the open block having one or more programmed word lines and one or more blank word lines, and in response to determining that the read disturbance level of the open block is beyond a threshold level, manage each memory cell in at least one of the blank word lines to have a smaller data storing capacity than each memory cell in at least one of the one or more programmed word lines so as to reduce impact of read disturbance.