中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

20 records (took 0.018 seconds)

    MANAGING BLOCK ARRANGEMENT OF SUPER BLOCKS
    1.
    发明申请
    MANAGING BLOCK ARRANGEMENT OF SUPER BLOCKS 审中-公开

    公开(公告)号：US20190179741A1

    公开(公告)日：2019-06-13

    申请号：US15836476

    申请日：2017-12-08

    Applicant: Macronix International Co., Ltd.

    Inventor： Ting-Yu Liu

    IPC: G06F12/02 ,  G06F12/06 ,  G11C29/00 ,  G06F11/10 ,  G06F3/06

    Abstract: Systems, methods, and apparatus including computer-readable mediums for managing block arrangement of super blocks in a memory such as NAND flash memory are provided. In one aspect, a memory controller for managing block arrangement of super blocks in a memory includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to maintain block information of each individual physical block in the planes and combine one or more physical blocks from the planes to a super block based on the block information of the physical blocks in the planes.

    Memory system and method for operating the same
    2.
    发明授权
    Memory system and method for operating the same 有权

    公开(公告)号：US10210097B2

    公开(公告)日：2019-02-19

    申请号：US15375545

    申请日：2016-12-12

    Applicant: Macronix International Co., Ltd.

    Inventor： Tzu-Yi Yang ,  Ting-Yu Liu ,  Yi-Chun Liu

    IPC: G06F12/121 ,  G06F3/06

    Abstract: A request is received to load a particular overlay segment from a secondary storage memory to a main memory for execution by a processor, wherein the particular overlay segment is absent from the main memory. A determination is made whether the main memory can receive the particular overlay segment. In response to determining that the main memory cannot receive the particular overlay segment, eviction strategy information about one or more existing overlay segments that are present in the main memory is obtained. Based on the eviction strategy information, at least one of the one or more existing overlay segments is selected for eviction from the main memory. The particular overlay segment is retrieved from the secondary storage memory. The at least one of the one or more existing overlay segments in the main memory that is selected for eviction is replaced with the particular overlay segment.

    Read performance of memory devices
    4.
    发明授权
    Read performance of memory devices 有权

    公开(公告)号：US11645006B2

    公开(公告)日：2023-05-09

    申请号：US16863202

    申请日：2020-04-30

    Applicant: Macronix International Co., Ltd.

    Inventor： Ting-Yu Liu ,  Yi-Chun Liu

    IPC: G06F3/06 ,  G06F12/123 ,  G06F12/10

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0674 ,  G06F12/10 ,  G06F12/124

    Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

    Memory device and method for accessing memory device with namespace management
    5.
    发明授权
    Memory device and method for accessing memory device with namespace management 有权

    公开(公告)号：US11614876B2

    公开(公告)日：2023-03-28

    申请号：US17408177

    申请日：2021-08-20

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Chang-Hao Chen ,  Ting-Yu Liu

    IPC: G06F3/06 ,  G06F12/0804 ,  G06F12/1009

    Abstract: The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a namespace table and an index table The processor obtains a data access command from a host device to determine whether a data of the data access command contains one of the NSIDs, assigns the at least one internal NSID to the data of the data access command according to the data access command in response to the data of the data access command that does not contain the namespace identifier, and, the processor manages the data with the internal NSID by the namespace table and the index table.

    MEMORY DEVICE AND METHOD FOR ACCESSING MEMORY DEVICE
    6.
    发明申请
    MEMORY DEVICE AND METHOD FOR ACCESSING MEMORY DEVICE 有权

    公开(公告)号：US20220374360A1

    公开(公告)日：2022-11-24

    申请号：US17323829

    申请日：2021-05-18

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Ting-Yu Liu ,  Chang-Hao Chen

    IPC: G06F12/0873 ,  G06F12/0891 ,  G06F12/02 ,  G06F12/123

    Abstract: The invention provides a memory device including a memory array, an internal memory, and a processor. The memory array stores node mapping tables for access data in the memory array. The internal memory includes a cached mapping table area and has a root mapping table. The processor determines whether a first node mapping table of the node mapping tables is temporarily stored in the cached mapping table area according to the root mapping table. In response to the first node mapping table is temporarily stored in the cached mapping table area, the processor accesses data according to the first node mapping table in the cached mapping table area, marks the modified first node mapping table through an asynchronous index identifier, and writes back the modified first node mapping table from the cached mapping table area to the memory array.

    MANAGING BLOCK ARRANGEMENT OF SUPER BLOCKS
    7.
    发明申请
    MANAGING BLOCK ARRANGEMENT OF SUPER BLOCKS 审中-公开

    公开(公告)号：US20200012596A1

    公开(公告)日：2020-01-09

    申请号：US16572922

    申请日：2019-09-17

    Applicant: Macronix International Co., Ltd.

    Inventor： Ting-Yu Liu

    IPC: G06F12/02 ,  G06F12/06 ,  G11C29/00 ,  G06F3/06 ,  G06F11/10

    Abstract: Systems, methods, and apparatus including computer-readable mediums for managing block arrangement of super blocks in a memory such as NAND flash memory are provided. In one aspect, a memory controller for managing block arrangement of super blocks in a memory includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to maintain block information of each individual physical block in the planes and select one or more physical blocks from the planes for a super block based on the block information of the physical blocks in the planes.

    Managing data arrangement in a super block
    8.
    发明授权
    Managing data arrangement in a super block 有权

    公开(公告)号：US10387243B2

    公开(公告)日：2019-08-20

    申请号：US15835859

    申请日：2017-12-08

    Applicant: Macronix International Co., Ltd.

    Inventor： Ting-Yu Liu ,  Yi-Chun Liu

    IPC: G06F12/00 ,  G06F11/10 ,  G06F3/06 ,  G06F12/02

    Abstract: Systems, methods, and apparatus including computer-readable mediums for managing data arrangement in a super block in a memory such as NAND flash memory are provided. In one aspect, a memory controller includes control circuitry coupled to the memory having at least two planes of physical blocks and configured to determine one or more characteristics of data to be written, allocate a super page of a super block based on the determined characteristics of the data and block information of the physical blocks of the planes, the super block combining one or more physical blocks from the planes, the super page combining one or more single pages from the corresponding one or more physical blocks in the super block, arrange the data to the one or more single pages in the super page, and program the super page to write the data in the one or more single pages.

    Read performance of memory devices
    10.
    发明授权
    Read performance of memory devices 有权

    公开(公告)号：US12086467B2

    公开(公告)日：2024-09-10

    申请号：US18175726

    申请日：2023-02-28

    Applicant: Macronix International Co., Ltd.

    Inventor： Ting-Yu Liu ,  Yi-Chun Liu

    IPC: G06F3/06 ,  G06F12/10 ,  G06F12/123

    CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0674 ,  G06F12/10 ,  G06F12/124

    Abstract: A memory controller managing a memory device receives a memory read command from a host device that is communicably coupled to the memory device. The memory device includes a storage memory comprising a first type of memory cells and a cache memory comprising a second type of memory cells. The memory controller determines, from the memory read command, a physical address of a target memory location in the storage memory indicated by the memory read command. The memory controller executes a read operation on the target memory location corresponding to the physical address. The memory controller determines a read attribute of the target memory location. Conditioned on determining that the read attribute satisfies one or more threshold conditions, the memory controller programs an entry in the cache memory with information corresponding to the target memory location.

Patent Agency Ranking