公开(公告)号：US09685233B2

公开(公告)日：2017-06-20

申请号：US14153934

申请日：2014-01-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Chang Hsieh ,  Ti-Wen Chen ,  Yung Chun Li ,  Kuo-Pin Chang

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14 ,  H01L27/11551 ,  H01L27/11578

Abstract: A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.