公开(公告)号：US09685233B2

公开(公告)日：2017-06-20

申请号：US14153934

申请日：2014-01-13

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Chang Hsieh ,  Ti-Wen Chen ,  Yung Chun Li ,  Kuo-Pin Chang

IPC: G11C16/10 ,  G11C11/56 ,  G11C16/34 ,  G11C16/04 ,  H01L27/11551 ,  H01L27/11578

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621 ,  G11C2216/14 ,  H01L27/11551 ,  H01L27/11578

Abstract: A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.

公开(公告)号：US08760928B2

公开(公告)日：2014-06-24

申请号：US13710992

申请日：2012-12-11

Applicant: Macronix International Co., Ltd

Inventor： Ti-Wen Chen ,  Hang-Ting Lue ,  Shuo-Nan Hung ,  Shih-Lin Huang ,  Chih-Chang Hsieh ,  Kuo-Pin Chang

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  G11C11/56 ,  G11C5/14

CPC classification number: G11C16/26 ,  G11C5/146 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/1157

Abstract: A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation.

Abstract translation: 电荷存储存储器配置在NAND阵列中，并且包括经由串选择开关耦合到位线的NAND串并且包括字线。 控制器被配置为产生用于对NAND阵列的所选单元执行操作的偏置。 该偏置包括在字符串选择开关闭合时对位线进行充电，例如不会将这种位线充电引起的噪声引入串中。 在耦合到所选字线的NAND串中的存储器单元的两侧的存储单元中的半导体主体区域被耦合到参考电压，使得它们被预充电，而阵列中的字符串的字线 在操作期间转变为各种电压。