公开(公告)号：US20200243121A1

公开(公告)日：2020-07-30

申请号：US16262770

申请日：2019-01-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Chu-Yung Liu ,  Hsing-Wen Chang ,  Yung-Hsiang Chen ,  Yao-Wen Chang

IPC: G11C7/10 ,  G11C8/08 ,  G11C7/12

Abstract: A non-volatile memory and a program method thereof are provided. The program method includes: selecting a programmed word line, where the programmed word line has a plurality of segments respectively corresponding to a plurality of bit lines; providing a program voltage to a voltage receiving end of the programmed word line, and sequentially transmitting the program voltage to the segments; respectively providing a plurality of bit line voltages to the bit lines at a plurality of enable time points and turning on a string selection switch at a setting time point; and setting voltage values of the bit line voltages according to the segments corresponding to the bit lines, respectively, or setting the enable time points according to the segments corresponding to the bit lines, or setting the setting time point according to a voltage transmission delay of the programmed word line.

公开(公告)号：US20200265896A1

公开(公告)日：2020-08-20

申请号：US16277877

申请日：2019-02-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsing-Wen Chang ,  Yao-Wen Chang

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/08

Abstract: A non-volatile memory and a program method thereof are provided. The program method includes: setting one of a plurality of word lines to be a program word line, setting the word lines except the program word line to be a plurality of unselected word lines; raise a voltage on the program word line from a reference voltage to a first program voltage during a first sub-time period of a program time period; raising the voltage on the program word line from the first program voltage to a second program voltage during a second sub-time period of the program time period; and raising voltages on at least part of the unselected word lines from the reference voltage to a pass voltage during the second sub-time period.

公开(公告)号：US10741250B1

公开(公告)日：2020-08-11

申请号：US16431913

申请日：2019-06-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hsing-Wen Chang ,  Yao-Wen Chang ,  Chi-Yuan Chin

IPC: G11C16/08 ,  G11C16/10 ,  H01L27/11582 ,  G11C16/34 ,  G11C16/04

Abstract: A non-volatile memory device driving method, applicable to a non-volatile memory device comprising a row decoder and a memory array, comprises: utilizing the row decoder to transmit multiple word line signals to multiple word lines of the memory array; according to an address, utilizing the row decoder to switch a selected word line signal of the multiple word line signals from a predetermined voltage level to a program voltage level; utilizing the row decoder to switch at least one support word line signal of the multiple word line signals from the predetermined voltage level to a first pass voltage level; when the selected word line signal is remained at the program voltage level, utilizing the row decoder to switch the at least one support word line signal from the first pass voltage level to a higher second pass voltage level.

公开(公告)号：US20250056816A1

公开(公告)日：2025-02-13

申请号：US18780515

申请日：2024-07-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Yung-Hsiang Chen ,  I-Chen Yang ,  Hsing-Wen Chang ,  Yao-Wen Chang

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a plurality of first peripheral circuits, a stack memory cell array and a first address circuit. The first peripheral circuits are disposed on a first chip, wherein the first chip has a plurality of first pads. The stack memory cell array is disposed on a second chip, wherein the second chip has a plurality of second pads. The second pads are coupled to the stack memory cell array, and respectively coupled to corresponding first pads. The first address circuit is disposed on the second chip, coupled to the stack memory cell array, and disposed under the stack memory cell array.

公开(公告)号：US10770144B1

公开(公告)日：2020-09-08

申请号：US16277877

申请日：2019-02-15

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsing-Wen Chang ,  Yao-Wen Chang

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/08 ,  H01L27/115

Abstract: A non-volatile memory and a program method thereof are provided. The program method includes: setting one of a plurality of word lines to be a program word line, setting the word lines except the program word line to be a plurality of unselected word lines; raise a voltage on the program word line from a reference voltage to a first program voltage during a first sub-time period of a program time period; raising the voltage on the program word line from the first program voltage to a second program voltage during a second sub-time period of the program time period; and raising voltages on at least part of the unselected word lines from the reference voltage to a pass voltage during the second sub-time period.

公开(公告)号：US09437303B1

公开(公告)日：2016-09-06

申请号：US14834809

申请日：2015-08-25

Applicant: MACRONIX International Co., Ltd.

Inventor： Chu-Yung Liu ,  Hsing-Wen Chang ,  Yao-Wen Chang ,  Tao-Cheng Lu

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3459

Abstract: A programming method of a memory array is provided and includes following steps, wherein the memory array includes a target memory cell and two periphery memory cells electrically connected to a first word line. After a first programming operation is performed on the target memory cell, the target memory cell and the two periphery memory cells are verified to obtain a first verification result. Whether to perform a second programming operation or a third programming operation on the target memory cell is determined according to the first verification result. The step of performing the second programming operation or the third programming operation on the target memory cell includes: turning off a first transistor and a second transistor; and increasing a level of a passing voltage for turning on a plurality of non-target memory cells and a level of a programming voltage transmitted by the first word line.

Abstract translation: 提供了存储器阵列的编程方法，并且包括以下步骤，其中存储器阵列包括电连接到第一字线的目标存储器单元和两个外围存储器单元。 在对目标存储单元执行第一编程操作之后，验证目标存储单元和两个周边存储单元以获得第一验证结果。 根据第一验证结果确定是否对目标存储单元执行第二编程操作或第三编程操作。 对目标存储单元执行第二编程操作或第三编程操作的步骤包括：关闭第一晶体管和第二晶体管; 以及增加用于接通多个非目标存储单元的通过电压的电平以及由第一字线发送的编程电压的电平。

公开(公告)号：US20140126296A1

公开(公告)日：2014-05-08

申请号：US14151617

申请日：2014-01-09

Applicant: MACRONIX International Co., Ltd.

Inventor： Hsing-Wen Chang ,  Yao-Wen Chang ,  Chu-Yung Liu

IPC: G11C16/08

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/3418

Abstract: A flash memory device including a memory array, a row decoder and M page buffers is provided, wherein M is an integer greater than 2. The memory array includes a plurality of memory cells and is connected to a plurality of word lines and a plurality of bit lines. The row decoder drives a specific word line among the word lines during an enabling period. Each of the page buffers is connected to N bit lines of the bit lines, and N is an integer equal to or greater than 3. A jth page buffer drives an (N*(j−1)+1)th bit line to an (N*j)th bit line during the enabling period, and one of an (i−1)th bit line and an (i+1)th bit line is not driven when an ith bit line is not driven, wherein j is an integer and 1≦j≦M, and i is an integer and 1

Abstract translation: 提供了包括存储器阵列，行解码器和M页缓冲器的闪速存储器件，其中M是大于2的整数。存储器阵列包括多个存储器单元，并且连接到多个字线和多个字线 位线。 行解码器在使能期间驱动字线中的特定字线。 每个页缓冲器连接到位线的N位线，N是等于或大于3的整数。第j页缓冲器驱动（N *（j-1）+1）位线到 （N * j）位线，并且当第i位线未被驱动时，不驱动第（i-1）位线和第（i + 1）位线之一，其中j为 整数和1＆nlE; j＆nlE; M，i是整数，1