公开(公告)号：US20200243121A1

公开(公告)日：2020-07-30

申请号：US16262770

申请日：2019-01-30

Applicant: MACRONIX International Co., Ltd.

Inventor： Chu-Yung Liu ,  Hsing-Wen Chang ,  Yung-Hsiang Chen ,  Yao-Wen Chang

IPC: G11C7/10 ,  G11C8/08 ,  G11C7/12

Abstract: A non-volatile memory and a program method thereof are provided. The program method includes: selecting a programmed word line, where the programmed word line has a plurality of segments respectively corresponding to a plurality of bit lines; providing a program voltage to a voltage receiving end of the programmed word line, and sequentially transmitting the program voltage to the segments; respectively providing a plurality of bit line voltages to the bit lines at a plurality of enable time points and turning on a string selection switch at a setting time point; and setting voltage values of the bit line voltages according to the segments corresponding to the bit lines, respectively, or setting the enable time points according to the segments corresponding to the bit lines, or setting the setting time point according to a voltage transmission delay of the programmed word line.

公开(公告)号：US20180158950A1

公开(公告)日：2018-06-07

申请号：US15371293

申请日：2016-12-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Hsiang Chen ,  Yao-Wen Chang ,  Chu-Yung Liu ,  I-Chen Yang ,  Hsin-Wen Chang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L27/088 ,  H01L27/112

CPC classification number: H01L29/7838 ,  H01L27/11286 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure includes a first source/drain region, a second source/drain region, a channel doping region, a gate structure, a first well and a second well. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. The first well has a first portion disposed under the first source/drain region. The second well is disposed opposite to the first well and separated from the second source/drain region. The first source/drain region, the second source/drain region and the channel doping region have a first conductive type. The first well and the second well have a second conductive type different from the first conductive type.

公开(公告)号：US10886405B2

公开(公告)日：2021-01-05

申请号：US15371293

申请日：2016-12-07

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Hsiang Chen ,  Yao-Wen Chang ,  Chu-Yung Liu ,  I-Chen Yang ,  Hsin-Wen Chang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L27/112 ,  H01L29/66 ,  H01L29/06

Abstract: A semiconductor structure includes a first source/drain region, a second source/drain region, a channel doping region, a gate structure, a first well and a second well. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. The first well has a first portion disposed under the first source/drain region. The second well is disposed opposite to the first well and separated from the second source/drain region. The first source/drain region, the second source/drain region and the channel doping region have a first conductive type. The first well and the second well have a second conductive type different from the first conductive type.

公开(公告)号：US20180144805A1

公开(公告)日：2018-05-24

申请号：US15358300

申请日：2016-11-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Hsiang Chen ,  Yao-Wen Chang ,  I-Chen Yang

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3422

Abstract: A method for operating a memory array is disclosed. The memory array includes a first memory cell, a second memory cell and a third memory cell sharing a gate and arranged along an extending direction of the gate in order. The method includes the following steps. A first bias is applied to a channel of the first memory cell to program the first memory cell. A second bias is applied to a channel of the second memory cell to inhibit programing of the second memory cell. A third bias is applied to a channel of the third memory cell to program or inhibit programing of the third memory cell. The first bias and the third bias are different.

公开(公告)号：US20250056816A1

公开(公告)日：2025-02-13

申请号：US18780515

申请日：2024-07-23

Applicant: MACRONIX International Co., Ltd.

Inventor： Yung-Hsiang Chen ,  I-Chen Yang ,  Hsing-Wen Chang ,  Yao-Wen Chang

IPC: H10B80/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a plurality of first peripheral circuits, a stack memory cell array and a first address circuit. The first peripheral circuits are disposed on a first chip, wherein the first chip has a plurality of first pads. The stack memory cell array is disposed on a second chip, wherein the second chip has a plurality of second pads. The second pads are coupled to the stack memory cell array, and respectively coupled to corresponding first pads. The first address circuit is disposed on the second chip, coupled to the stack memory cell array, and disposed under the stack memory cell array.

公开(公告)号：US09978457B1

公开(公告)日：2018-05-22

申请号：US15358300

申请日：2016-11-22

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Hsiang Chen ,  Yao-Wen Chang ,  I-Chen Yang

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3422

Abstract: A method for operating a memory array is disclosed. The memory array includes a first memory cell, a second memory cell and a third memory cell sharing a gate and arranged along an extending direction of the gate in order. The method includes the following steps. A first bias is applied to a channel of the first memory cell to program the first memory cell. A second bias is applied to a channel of the second memory cell to inhibit programming of the second memory cell. A third bias is applied to a channel of the third memory cell to program or inhibit programming of the third memory cell. The first bias and the third bias are different.

公开(公告)号：US20240243180A1

公开(公告)日：2024-07-18

申请号：US18153368

申请日：2023-01-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： I-Chen Yang ,  Chun Liang Lu ,  Yung-Hsiang Chen ,  Yao-Wen Chang

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L29/4238 ,  H01L29/66621 ,  H01L29/7833 ,  H01L29/66598

Abstract: A semiconductor device includes a substrate, a gate structure, a first doped region and a second doped region. The substrate has a plurality of recesses therein. A gate structure covers the plurality of recesses and a surface of the substrate between the plurality of recesses. The gate structure includes a gate dielectric layer and a gate conductive layer. The gate dielectric layer covers bottom surfaces and sidewalls of the plurality of recesses and the surface of the substrate between the plurality of recesses. The gate conductive layer is formed on the gate dielectric layer, fills in the plurality of recesses and covers the surface of the substrate between the plurality of recesses. The first doped region and the second doped region are located at two sides of the gate structure.

公开(公告)号：US20190035930A1

公开(公告)日：2019-01-31

申请号：US15664010

申请日：2017-07-31

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yung-Hsiang Chen ,  I-Chen Yang

IPC: H01L29/78 ,  H01L29/08 ,  H01L21/266

Abstract: A semiconductor structure includes a substrate, a first source/drain region, a second source/drain region, a channel doping region and a gate structure. The first source/drain region is disposed in the substrate. The first source/drain region includes a first region and a second region under the first region. The second source/drain region is disposed in the substrate. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed in the substrate between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. In a projection plane parallel to the top surface of the substrate, the second region of the first source/drain region is separated from the gate structure. The first source/drain region, the second source/drain region and the channel doping region have the same conductive type.