公开(公告)号：US20170205772A1

公开(公告)日：2017-07-20

申请号：US15370796

申请日：2016-12-06

Applicant: Marvell World Trade Ltd.

Inventor： Olivier BURG ,  Haisong WANG ,  Xiang GAO

IPC: G04F10/00

CPC classification number: G04F10/005 ,  H03B21/02 ,  H03L7/0891 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/18 ,  H03M1/00 ,  H03M1/12 ,  H03M1/50 ,  H03M7/3004 ,  H03M2201/4233 ,  H04M1/505

Abstract: A digital phase locked loop (DPLL) circuit includes a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal and a time-to-digital converter (TDC) coupled to an output of the DTC. The TDC is configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal. A method of controlling a DPLL includes delaying a reference clock signal according to a delay control signal, sampling a value of a transition signal according to the delayed reference clock signal, generating an output signal indicating a phase difference between the delayed clock signal and an input clock signal, and generating a digitally controlled oscillator (DCO) clock signal according to the output signal.

公开(公告)号：US20130271229A1

公开(公告)日：2013-10-17

申请号：US13861125

申请日：2013-04-11

Applicant: MARVELL WORLD TRADE LTD

Inventor： Xiang GAO ,  Chi-Hung Lin ,  Li Lin

IPC: H03L7/06

CPC classification number: H03L7/06 ,  H03L7/23

Abstract: Aspects of the disclosure provide a local oscillator (LO) circuit that includes a first phase locked loop (PLL) circuit and a second PLL. The first PLL circuit is configured to generate a first oscillation signal having a first frequency based on a reference signal having a reference frequency. The second PLL circuit is configured to receive the first oscillation signal and generate a second oscillation signal having a second frequency based on the first oscillation signal.

Abstract translation: 本公开的方面提供了包括第一锁相环（PLL）电路和第二PLL的本地振荡器（LO）电路。 第一PLL电路被配置为基于具有参考频率的参考信号产生具有第一频率的第一振荡信号。 第二PLL电路被配置为接收第一振荡信号并且基于第一振荡信号产生具有第二频率的第二振荡信号。

公开(公告)号：US20150130544A1

公开(公告)日：2015-05-14

申请号：US14540485

申请日：2014-11-13

Applicant: MARVELL WORLD TRADE LTD

Inventor： Xiang GAO ,  Li Lin

IPC: H03L7/18

CPC classification number: H03L7/18 ,  H03L7/085 ,  H03L7/091 ,  H03L7/099 ,  H03L7/0992 ,  H03L7/183 ,  H03L7/197

Abstract: Aspects of the disclosure provide a circuit that includes a detector, a loop filter and a controller. The detector is configured to generate a first signal indicative a timing difference between a reference clock signal and a feedback clock signal. The feedback clock signal is generated based on an oscillating signal from an oscillator. The oscillator includes a first tuning circuit and a second tuning circuit to tune a frequency of the oscillating signal. The loop filter is configured to filter out a portion of frequency components from the first signal to generate a second signal for tuning the first tuning circuit of the oscillator. The controller is configured to tune the second tuning circuit based on the first signal and the second signal.

Abstract translation: 本公开的方面提供了一种包括检测器，环路滤波器和控制器的电路。 检测器被配置为产生指示参考时钟信号和反馈时钟信号之间的定时差的第一信号。 基于来自振荡器的振荡信号产生反馈时钟信号。 振荡器包括第一调谐电路和调谐振荡信号的频率的第二调谐电路。 环路滤波器被配置为从第一信号滤出一部分频率分量以产生用于调谐振荡器的第一调谐电路的第二信号。 控制器被配置为基于第一信号和第二信号来调谐第二调谐电路。