公开(公告)号：US20150144878A1

公开(公告)日：2015-05-28

申请号：US14550272

申请日：2014-11-21

申请人： MEARS Technologies, Inc.

发明人： Robert Mears ,  Hideki Takeuchi ,  Erwin Trautmann

IPC分类号： H01L29/10 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/1054 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/1079 ,  H01L29/15 ,  H01L29/155 ,  H01L29/16 ,  H01L29/66431 ,  H01L29/66477 ,  H01L29/66575 ,  H01L29/78

摘要： A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.

摘要翻译： 半导体器件可以包括在衬底上的超晶格和体半导体层的交替堆叠，其中每个超晶格层包括多个堆叠的层组，并且超晶格层的每组层包括多个层叠的基底半导体单层， 基底半导体部分和限制在相邻基极半导体部分的晶格内的至少一个非半导体单层。 该半导体器件还可包括在超晶格和体半导体层的交替叠层的上部体半导体层中的间隔开的源极和漏极区域，以及位于间隔开的源极和漏极区域之间的上体积半导体层上的栅极。

公开(公告)号：US20150144877A1

公开(公告)日：2015-05-28

申请号：US14550244

申请日：2014-11-21

申请人： MEARS Technologies, Inc.

发明人： Robert Mears ,  Hideki Takeuchi ,  Erwin Trautmann

IPC分类号： H01L27/088 ,  H01L21/324 ,  H01L29/165 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/15

CPC分类号： H01L29/152 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0638 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/155 ,  H01L29/165 ,  H01L29/66537 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.

摘要翻译： 半导体器件可以包括衬底和在衬底上间隔开的多个散热片。 每个翅片可以包括从基底垂直向上延伸的下半导体翅片部分，以及在下翅片部分上的至少一个超晶格穿通层。 超晶格穿通层可以包括多个堆叠的层组，超晶格穿透层的每组层包括限定基极半导体部分的多个堆叠的基底半导体单层和至少一个非半导体单层约束 在相邻的基底半导体部分的晶格内。 每个翅片还可以包括在至少一个超晶格穿通层上并从其垂直向上延伸的上半导体翅片部分。 半导体器件还可以包括在鳍片的相对端处的源极和漏极区域以及覆盖鳍片的栅极。

公开(公告)号：US09275996B2

公开(公告)日：2016-03-01

申请号：US14550244

申请日：2014-11-21

申请人： MEARS Technologies, Inc.

发明人： Robert Mears ,  Hideki Takeuchi ,  Erwin Trautmann

IPC分类号： H01L21/336 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/15 ,  H01L29/165

CPC分类号： H01L29/152 ,  H01L21/324 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0638 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/155 ,  H01L29/165 ,  H01L29/66537 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.

摘要翻译： 半导体器件可以包括衬底和在衬底上间隔开的多个散热片。 每个翅片可以包括从基底垂直向上延伸的下半导体翅片部分，以及在下翅片部分上的至少一个超晶格穿通层。 超晶格穿通层可以包括多个堆叠的层组，超晶格穿透层的每组层包括限定基极半导体部分的多个堆叠的基底半导体单层和至少一个非半导体单层约束 在相邻的基底半导体部分的晶格内。 每个翅片还可以包括在至少一个超晶格穿通层上并从其垂直向上延伸的上半导体翅片部分。 半导体器件还可以包括在鳍片的相对端处的源极和漏极区域以及覆盖鳍片的栅极。