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1.发明申请公开(公告)号：US20160099317A1
公开(公告)日：2016-04-07
申请号：US14958447
申请日：2015-12-03
发明人： ROBERT MEARS , HIDEKI TAKEUCHI , ERWIN TRAUTMANN
IPC分类号： H01L29/15 , H01L29/06 , H01L29/78 , H01L29/165
CPC分类号： H01L29/152 , H01L21/324 , H01L21/823412 , H01L21/823431 , H01L27/0886 , H01L29/0638 , H01L29/1054 , H01L29/1083 , H01L29/155 , H01L29/165 , H01L29/66537 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.
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2.发明申请SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE DEPLETION LAYER STACK AND RELATED METHODS 有权半导体器件，包括超滤层堆叠及相关方法公开(公告)号：US20150144878A1
公开(公告)日：2015-05-28
申请号：US14550272
申请日：2014-11-21
发明人： Robert Mears , Hideki Takeuchi , Erwin Trautmann
IPC分类号： H01L29/10 , H01L27/092 , H01L29/78 , H01L29/66 , H01L21/8238
CPC分类号： H01L29/1054 , H01L21/76224 , H01L21/76283 , H01L21/8238 , H01L21/823807 , H01L21/823878 , H01L21/823892 , H01L27/092 , H01L29/0649 , H01L29/1079 , H01L29/15 , H01L29/155 , H01L29/16 , H01L29/66431 , H01L29/66477 , H01L29/66575 , H01L29/78
摘要： A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.
摘要翻译： 半导体器件可以包括在衬底上的超晶格和体半导体层的交替堆叠，其中每个超晶格层包括多个堆叠的层组，并且超晶格层的每组层包括多个层叠的基底半导体单层， 基底半导体部分和限制在相邻基极半导体部分的晶格内的至少一个非半导体单层。 该半导体器件还可包括在超晶格和体半导体层的交替叠层的上部体半导体层中的间隔开的源极和漏极区域，以及位于间隔开的源极和漏极区域之间的上体积半导体层上的栅极。
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3.发明申请SEMICONDUCTOR DEVICE INCLUDING A SUPERLATTICE AND REPLACEMENT METAL GATE STRUCTURE AND RELATED METHODS 有权包括超级和替代金属门结构的半导体器件及相关方法公开(公告)号：US20160149023A1
公开(公告)日：2016-05-26
申请号：US14948547
申请日：2015-11-23
IPC分类号： H01L29/778 , H01L29/66 , H01L29/06 , H01L29/15
CPC分类号： H01L29/154 , H01L29/0642 , H01L29/0653 , H01L29/1054 , H01L29/1083 , H01L29/152 , H01L29/155 , H01L29/165 , H01L29/66431 , H01L29/66545 , H01L29/66621 , H01L29/7782
摘要： A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.
摘要翻译： 半导体器件可以包括其中具有沟道凹槽的衬底，衬底中的多个间隔开的浅沟槽隔离（STI）区域，以及在衬底中和在一对STI区域之间间隔开的源极和漏极区域。 超晶格通道可以在衬底的通道凹槽中并且在源极和漏极区域之间延伸，超晶格通道包括多个堆叠的层组，并且超晶格沟道的每组层包括层叠的基底半导体单层，其定义为 基底半导体部分和限制在相邻基极半导体部分的晶格内的至少一个非半导体单层。 替代门可能超过超晶格通道。
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4.发明申请VERTICAL SEMICONDUCTOR DEVICES INCLUDING SUPERLATTICE PUNCH THROUGH STOP LAYER AND RELATED METHODS 有权垂直半导体器件，包括通过停止层的超级激励器及相关方法公开(公告)号：US20150144877A1
公开(公告)日：2015-05-28
申请号：US14550244
申请日：2014-11-21
发明人： Robert Mears , Hideki Takeuchi , Erwin Trautmann
IPC分类号： H01L27/088 , H01L21/324 , H01L29/165 , H01L29/10 , H01L21/8234 , H01L29/15
CPC分类号： H01L29/152 , H01L21/324 , H01L21/823412 , H01L21/823431 , H01L27/0886 , H01L29/0638 , H01L29/1054 , H01L29/1083 , H01L29/155 , H01L29/165 , H01L29/66537 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.
摘要翻译： 半导体器件可以包括衬底和在衬底上间隔开的多个散热片。 每个翅片可以包括从基底垂直向上延伸的下半导体翅片部分，以及在下翅片部分上的至少一个超晶格穿通层。 超晶格穿通层可以包括多个堆叠的层组，超晶格穿透层的每组层包括限定基极半导体部分的多个堆叠的基底半导体单层和至少一个非半导体单层约束 在相邻的基底半导体部分的晶格内。 每个翅片还可以包括在至少一个超晶格穿通层上并从其垂直向上延伸的上半导体翅片部分。 半导体器件还可以包括在鳍片的相对端处的源极和漏极区域以及覆盖鳍片的栅极。
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5.发明申请SEMICONDUCTOR DEVICES WITH ENHANCED DETERMINISTIC DOPING AND RELATED METHODS 有权具有增强决定性掺杂的半导体器件及相关方法公开(公告)号：US20150357414A1
公开(公告)日：2015-12-10
申请号：US14734412
申请日：2015-06-09
发明人： Robert J. MEARS
IPC分类号： H01L29/15 , H01L29/167 , H01L21/324 , H01L21/02 , H01L21/265
CPC分类号： H01L29/152 , H01L21/02507 , H01L21/26513 , H01L21/2652 , H01L21/324 , H01L29/151 , H01L29/167
摘要： A method for making a semiconductor device may include forming a plurality of stacked groups of layers on a semiconductor substrate, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include implanting a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region, and performing an anneal of the plurality of stacked groups of layers and semiconductor substrate and with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region.
摘要翻译： 制造半导体器件的方法可以包括在半导体衬底上形成多个堆叠的层组，其中每组层包括限定基底半导体部分的多个堆叠的基底半导体单层和限定在其中的至少一个非半导体单层 相邻的基底半导体部分的晶格。 该方法还可以包括在半导体衬底中的至少一个局部区域中的多个层叠组下方的半导体衬底内注入掺杂剂，并且执行多个层叠的层和半导体衬底组的退火， 垂直和水平地限制所述至少一个局部区域中的掺杂剂的层。
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6.发明授权Vertical semiconductor devices including superlattice punch through stop layer and related methods 有权垂直半导体器件包括超晶格穿通止动层及相关方法公开(公告)号：US09275996B2
公开(公告)日：2016-03-01
申请号：US14550244
申请日：2014-11-21
发明人： Robert Mears , Hideki Takeuchi , Erwin Trautmann
IPC分类号： H01L21/336 , H01L27/088 , H01L29/66 , H01L29/78 , H01L29/10 , H01L21/324 , H01L21/8234 , H01L29/15 , H01L29/165
CPC分类号： H01L29/152 , H01L21/324 , H01L21/823412 , H01L21/823431 , H01L27/0886 , H01L29/0638 , H01L29/1054 , H01L29/1083 , H01L29/155 , H01L29/165 , H01L29/66537 , H01L29/66795 , H01L29/785 , H01L29/7851
摘要： A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.
摘要翻译： 半导体器件可以包括衬底和在衬底上间隔开的多个散热片。 每个翅片可以包括从基底垂直向上延伸的下半导体翅片部分，以及在下翅片部分上的至少一个超晶格穿通层。 超晶格穿通层可以包括多个堆叠的层组，超晶格穿透层的每组层包括限定基极半导体部分的多个堆叠的基底半导体单层和至少一个非半导体单层约束 在相邻的基底半导体部分的晶格内。 每个翅片还可以包括在至少一个超晶格穿通层上并从其垂直向上延伸的上半导体翅片部分。 半导体器件还可以包括在鳍片的相对端处的源极和漏极区域以及覆盖鳍片的栅极。
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