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公开(公告)号：US10476456B2
公开(公告)日：2019-11-12
申请号：US15465667
申请日：2017-03-22
Applicant: MediaTek Inc.
Inventor： Ayman Shabra , Michael A. Ashburn, Jr.
Abstract: A comparator is described. The comparator may be used in several applications, including in digital-to-analog converters (ADC). The comparator may comprise a high-speed amplifier, a low-noise amplifier, a controller and a bi-stable circuit. The high-speed amplifier may be activated during a first period, for example when the comparator tends to exhibit a slow response. During this period, the comparator may sacrifice the noise performance. The low-noise amplifier may be activated during a second period, for example when the difference between the signals appearing as inputs to the comparator is small. The low-noise amplifier may have a gain that is large enough to limit decision errors. The bi-stable circuit, which may be implemented using a latch, may be configured to output a signal equal to one of the supply voltages, in response to receiving the input signal from one of the stages.
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公开(公告)号：US10075180B2
公开(公告)日：2018-09-11
申请号：US15809476
申请日：2017-11-10
Applicant: MediaTek Inc.
Inventor： Tao He , Michael A. Ashburn, Jr.
Abstract: Circuits and methods for inter-symbol interference compensation are described. These circuits and methods may be used in connection with delta-sigma analog-to-digital converter. During a sensing phase, a value indicative of the inter-symbol interference may be sensed. The value may be obtained by (1) causing the ADC to generate a first number of transitions during a first time interval; (2) causing the ADC to generate a second number of transitions during a second time interval; (3) sensing the number of logic-0s and logic-1s occurring in the first and second time intervals; and (4) computing the value based at least in part on the number of logic-0s and logic-1s occurring in the first and second time intervals. During a compensation phase, inter-symbol interference may be compensated based on the value obtained in the sensing phase.
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公开(公告)号：US09634687B2
公开(公告)日：2017-04-25
申请号：US15069951
申请日：2016-03-14
Applicant: MEDIATEK INC.
Inventor： Sheng-Jui Huang , Michael A. Ashburn, Jr. , Divya Kesharwani , Nathan Egan
IPC: H03M3/00
Abstract: A continuous-time sigma-delta modulator includes a VCO-based quantizer, a rotator, a truncation circuit and a digital-to-analog converter (DAC). The VCO-based quantizer is arranged to generate a thermometer code based on an input signal and a feedback signal. The rotator is coupled to the VCO-based quantizer, and is arranged to generate a phase-shifted thermometer code based on the thermometer code and a phase shift, and generate a rearranged thermometer code based on the phase-shifted thermometer code to comply with a specific pattern. The truncation circuit is coupled to the rotator, and is arranged to extract a most significant bit (MSB) part from the rearranged thermometer code. The DAC is coupled to the truncation circuit, and is arranged to generate the feedback signal according to at least the MSB part. Two alternative continuous-time sigma-delta modulators are also disclosed.
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公开(公告)号：US09461660B2
公开(公告)日：2016-10-04
申请号：US14938567
申请日：2015-11-11
Applicant: Mediatek Inc.
Inventor： Khurram Muhammad , Chi-Lun Lo , Frank Op 't Eynde , Michael A. Ashburn, Jr. , Tien-Yu Lo
CPC classification number: H03M1/0626 , H03M1/1255 , H03M1/60
Abstract: A method and apparatus for a digitally-corrected analog-to-digital converter (ADC) are disclosed. The apparatus comprises a nonlinearity generator that generates one or more nonlinear characteristics of a time varying input signal and that causes unwanted signal components at frequencies other than a frequency of the time varying input signal, a frequency response modifier coupled to the nonlinearity generator that modifies the unwanted signal components by altering an amplitude of the unwanted signal components, a frequency response compensator coupled to the frequency response modifier, wherein the frequency response compensator compensates for the modification introduced by the frequency response modifier to provide a filtered digital signal, and an inverse nonlinearity generator coupled to the frequency response compensator for receiving the filtered digital signal, wherein the inverse nonlinearity generator compensates for the one or more nonlinear characteristics.
Abstract translation: 公开了一种用于数字校正的模数转换器（ADC）的方法和装置。 该装置包括非线性发生器，其产生时变输入信号的一个或多个非线性特性，并且在不同于时变输入信号的频率的频率下产生不想要的信号分量，耦合到非线性发生器的频率响应修改器， 通过改变不需要的信号分量的幅度的不需要的信号分量，耦合到频率响应修改器的频率响应补偿器，其中频率响应补偿器补偿由频率响应修改器引入的修改以提供经滤波的数字信号，以及反向非线性 耦合到频率响应补偿器的发生器，用于接收经滤波的数字信号，其中逆非线性发生器补偿一个或多个非线性特性。
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