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公开(公告)号：US20190250924A1
公开(公告)日：2019-08-15
申请号：US16395193
申请日：2019-04-25
Applicant: MediaTek Inc.
Inventor： Shou-Jen Lai , Pei-Kuei Tsung , Po-Chun Fan , Sung-Fang Tsai
CPC classification number: G06F9/3887 , G06F9/30036 , G06F9/3012 , G06F9/3824 , G06F9/383 , G06F9/3851
Abstract: A computing device operative to perform parallel computations. The computing device includes a controller unit to assign workgroups to a set of batches. Each batch includes a program counter shared by M workgroups assigned to the batch, where M is a positive integer determined according to a configurable batch setting. Each batch further includes a set of thread processing units operative to execute, in parallel, a subset of work items in each of the M workgroups. Each batch further includes a spilling memory to store intermediate data of the M workgroups when one or more workgroups in the M workgroups encounters a synchronization barrier.
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公开(公告)号：US10324730B2
公开(公告)日：2019-06-18
申请号：US15285472
申请日：2016-10-04
Applicant: MediaTek Inc.
Inventor： Shou-Jen Lai , Pei-Kuei Tsung , Po-Chun Fan , Sung-Fang Tsai
Abstract: A computing device performs parallel computations using a set of thread processing units and a memory shuffle engine. The memory shuffle engine includes a register array to store an array of data elements retrieved from a memory buffer, and an array of input selectors. According to a first control signal, each input selector transfers at least a first data element from a corresponding subset of the register array, which is coupled to the input selector via input lines, to one or more corresponding thread processing units. According to a second control signal, each input selector transfers at least a second data element from another subset of the register array, which is coupled to another input selector via other input lines, to the one or more corresponding thread processing units.
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3.发明申请公开(公告)号：US20170262291A1
公开(公告)日：2017-09-14
申请号：US15065447
申请日：2016-03-09
Applicant: MediaTek Inc.
Inventor： Shou-Jen Lai , Pei-Kuei Tsung , Sung-Fang Tsai
CPC classification number: G06F9/50 , G06F9/3877
Abstract: A heterogeneous computing system described herein includes a parallel processing module shared among a set of heterogeneous processors. The processors have different processor types, and each processor includes an internal memory unit to store its current context. The parallel processing module includes multiple execution units. A switch module is coupled to the processors and the parallel processing module. The switch module is operative to select, according to a control signal, one of the processors to use the parallel processing module for executing an instruction with multiple data entries in parallel.
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公开(公告)号：US11175920B2
公开(公告)日：2021-11-16
申请号：US16395193
申请日：2019-04-25
Applicant: MediaTek Inc.
Inventor： Shou-Jen Lai , Pei-Kuei Tsung , Po-Chun Fan , Sung-Fang Tsai
Abstract: A computing device operative to perform parallel computations. The computing device includes a controller unit to assign workgroups to a set of batches. Each batch includes a program counter shared by M workgroups assigned to the batch, where M is a positive integer determined according to a configurable batch setting. Each batch further includes a set of thread processing units operative to execute, in parallel, a subset of work items in each of the M workgroups. Each batch further includes a spilling memory to store intermediate data of the M workgroups when one or more workgroups in the M workgroups encounters a synchronization barrier.
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5.发明授权公开(公告)号：US09836869B2
公开(公告)日：2017-12-05
申请号：US15075050
申请日：2016-03-18
Applicant: MediaTek Inc.
Inventor： Sung-Fang Tsai , Pei-Kuei Tsung , Ming-Hao Liao
CPC classification number: G06T15/005 , G06T11/40
Abstract: A graphics-processing method and a graphics-processing apparatus are provided. The graphics-processing method includes the steps of computing a vertex position of a vertex in a binning phase to obtain a first position data; generating a first signal according to a first condition, wherein when the first signal corresponds to a first value, the first position data is stored into a memory unit, and when the first signal corresponds to a second value, the vertex position of the vertex in a rendering phase is computed to obtain a second position data; computing a vertex varying of the vertex in the binning phase or the rendering phase; and rendering in the rendering phase according to either the first position data or the second position data.
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Patent Agency Ranking
公开(公告)号：US20170277567A1
公开(公告)日：2017-09-28
申请号：US15285472
申请日：2016-10-04
Applicant: MediaTek Inc.
Inventor： Shou-Jen Lai , Pei-Kuei Tsung , Po-Chun Fan , Sung-Fang Tsai
CPC classification number: G06F9/3887 , G06F9/30036 , G06F9/3012 , G06F9/3824 , G06F9/3851
Abstract: A computing device performs parallel computations using a set of thread processing units and a memory shuffle engine. The memory shuffle engine includes a register array to store an array of data elements retrieved from a memory buffer, and an array of input selectors. According to a first control signal, each input selector transfers at least a first data element from a corresponding subset of the register array, which is coupled to the input selector via input lines, to one or more corresponding thread processing units. According to a second control signal, each input selector transfers at least a second data element from another subset of the register array, which is coupled to another input selector via other input lines, to the one or more corresponding thread processing units.
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公开(公告)号：US20180173676A1
公开(公告)日：2018-06-21
申请号：US15787897
申请日：2017-10-19
Applicant: MediaTek Inc.
Inventor： Sung-Fang Tsai , Pei-Kuei Tsung , Po-Chun Fan , Shou-Jen Lai
CPC classification number: G06F17/15 , G06F17/16 , G06N3/0454 , G06N3/063
Abstract: A system performs convolution computing in either a matrix mode or a filter mode. An analysis module generates a mode select signal to select the matrix mode or the filter mode based on results of analyzing convolution characteristics. The results include at least a comparison of resource utilization between the matrix mode and the filter mode. A convolution module includes processing elements, each of which further includes arithmetic computing circuitry. The convolution module is configured according to the matrix mode for performing matrix multiplications converted from convolution computations, and is configured according to the filter mode for performing the convolution computations.
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公开(公告)号：US20180173463A1
公开(公告)日：2018-06-21
申请号：US15675710
申请日：2017-08-12
Applicant: MediaTek Inc.
Inventor： Po-Chun Fan , Pei-Kuei Tsung , Sung-Fang Tsai , Chia-Hsien Chou , Shou-Jen Lai
CPC classification number: G06F3/0659 , G06F3/0611 , G06F3/0685 , G06F12/0638 , G06F12/0806 , G06F2212/1024 , G06F2212/205
Abstract: A system is provided to manage on-chip memory access for multiple threads. The system comprises multiple parallel processing units to execute the threads, and an on-chip memory including multiple memory units and each memory unit includes a first region and a second region. The first region and the second region have different memory addressing schemes for parallel access by the threads. The system further comprises an address decoder coupled to the parallel processing units and the on-chip memory. The address decoder is operative to activate access by the threads to memory locations in the first region or the second region according to decoded address signals from the parallel processing units.
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公开(公告)号：US20150332495A1
公开(公告)日：2015-11-19
申请号：US14675759
申请日：2015-04-01
Applicant: MEDIATEK INC.
Inventor： Ming-Hao Liao , Sung-Fang Tsai , Pei-Kuei Tsung , Hung-Wei Wu
IPC: G06T15/00
CPC classification number: G06T15/005 , G06T11/40
Abstract: A graphics processing method and an associated graphics processing apparatus are provided, where the graphics processing method is applied to the graphics processing apparatus, the graphics processing apparatus may be positioned within an electronic device, and the graphics processing apparatus may comprise at least one portion of the electronic device. The graphics processing method includes the steps of: calculating vertex positions of a primitive in a binning phase; determining, according to specific information, whether to compute vertex varyings of the primitive in the binning phase or in a rendering phase so as to provide a determination result; computing the vertex varyings in the binning phase or in the rendering phase according to the determination result; and rendering the primitive according to the vertex positions and the vertex varyings in the rendering phase.
Abstract translation: 提供了图形处理方法和相关联的图形处理装置，其中将图形处理方法应用于图形处理装置，图形处理装置可以位于电子装置内，并且图形处理装置可以包括至少一部分 电子设备。 图形处理方法包括以下步骤：计算合并阶段中原语的顶点位置; 根据具体信息确定是否计算合并阶段或渲染阶段中的原语的顶点变化，以便提供确定结果; 根据确定结果计算合并阶段或渲染阶段中的顶点变化; 并根据渲染阶段中的顶点位置和顶点变化渲染图元。
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公开(公告)号：US10394929B2
公开(公告)日：2019-08-27
申请号：US15787897
申请日：2017-10-19
Applicant: MediaTek Inc.
Inventor： Sung-Fang Tsai , Pei-Kuei Tsung , Po-Chun Fan , Shou-Jen Lai
Abstract: A system performs convolution computing in either a matrix mode or a filter mode. An analysis module generates a mode select signal to select the matrix mode or the filter mode based on results of analyzing convolution characteristics. The results include at least a comparison of resource utilization between the matrix mode and the filter mode. A convolution module includes processing elements, each of which further includes arithmetic computing circuitry. The convolution module is configured according to the matrix mode for performing matrix multiplications converted from convolution computations, and is configured according to the filter mode for performing the convolution computations.
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