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公开(公告)号：US20230176645A1
公开(公告)日：2023-06-08
申请号：US17866483
申请日：2022-07-16
Applicant: MediaTek Inc.
Inventor： Hung-Wei Wu , Chih-Yu Chang
IPC: G06F1/3296 , G06F1/3206
CPC classification number: G06F1/3296 , G06F1/3206
Abstract: A management circuit is coupled to multiple processor cores for performing current suppression. The management circuit includes a detection circuit and a throttle signal generator. The detection circuit is operative to receive an activity signal from each processor core, and estimate a total current consumed by the plurality of processor cores based on activity signals. The activity signal indicates a current index proportional to current consumption of the processor core in a given time period. The throttle signal generator is operative to assert or de-assert throttle signals to the processor cores, one processor core at a time, based on one or more metrics calculated from the total current.
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2.发明申请APPARATUS AND METHOD FOR CONTROLLING EARLY DEPTH PROCESSING AND POST DEPTH PROCESSING 有权用于控制早期深度处理和深度处理的装置和方法公开(公告)号：US20160005208A1
公开(公告)日：2016-01-07
申请号：US14642763
申请日：2015-03-10
Applicant: Mediatek Inc.
Inventor： Ming-Hao Liao , Tsung-Liang Hou , Chin-Yuan Yao , Hung-Wei Wu
CPC classification number: G06T15/005 , G06T15/405
Abstract: A depth processing apparatus includes a depth buffer, an early depth processing circuit, a post depth processing circuit, and a depth processing controller. The depth buffer stores depth information of a plurality of pixels of a screen space. The early depth processing circuit performs early depth processing based on at least a portion of the depth information before a pixel shading stage. The post depth processing circuit performs post depth processing based on at least a portion of the depth information after the pixel shading stage. The depth processing controller manages a plurality of dependency indication values corresponding to a plurality of sub-regions in the screen space, respectively, and configured to control a first pixel for undergoing at least one of the early depth processing and the post depth processing by referring a first dependency indication value of a first sub-region in which the first pixel is located.
Abstract translation: 深度处理装置包括深度缓冲器，早期深度处理电路，后深度处理电路和深度处理控制器。 深度缓冲器存储屏幕空间的多个像素的深度信息。 早期深度处理电路基于像素着色阶段之前的深度信息的至少一部分来执行早期深度处理。 后深度处理电路基于像素着色阶段之后的深度信息的至少一部分来执行后深度处理。 深度处理控制器分别管理与屏幕空间中的多个子区域相对应的多个相关性指示值，并且被配置为控制用于通过参考来进行早期深度处理和后深度处理中的至少一个的第一像素 第一像素所在的第一子区域的第一依赖性指示值。
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公开(公告)号：US20150332495A1
公开(公告)日：2015-11-19
申请号：US14675759
申请日：2015-04-01
Applicant: MEDIATEK INC.
Inventor： Ming-Hao Liao , Sung-Fang Tsai , Pei-Kuei Tsung , Hung-Wei Wu
IPC: G06T15/00
CPC classification number: G06T15/005 , G06T11/40
Abstract: A graphics processing method and an associated graphics processing apparatus are provided, where the graphics processing method is applied to the graphics processing apparatus, the graphics processing apparatus may be positioned within an electronic device, and the graphics processing apparatus may comprise at least one portion of the electronic device. The graphics processing method includes the steps of: calculating vertex positions of a primitive in a binning phase; determining, according to specific information, whether to compute vertex varyings of the primitive in the binning phase or in a rendering phase so as to provide a determination result; computing the vertex varyings in the binning phase or in the rendering phase according to the determination result; and rendering the primitive according to the vertex positions and the vertex varyings in the rendering phase.
Abstract translation: 提供了图形处理方法和相关联的图形处理装置，其中将图形处理方法应用于图形处理装置，图形处理装置可以位于电子装置内，并且图形处理装置可以包括至少一部分 电子设备。 图形处理方法包括以下步骤：计算合并阶段中原语的顶点位置; 根据具体信息确定是否计算合并阶段或渲染阶段中的原语的顶点变化，以便提供确定结果; 根据确定结果计算合并阶段或渲染阶段中的顶点变化; 并根据渲染阶段中的顶点位置和顶点变化渲染图元。
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公开(公告)号：US11989077B2
公开(公告)日：2024-05-21
申请号：US17866483
申请日：2022-07-16
Applicant: MediaTek Inc.
Inventor： Hung-Wei Wu , Chih-Yu Chang
IPC: G06F1/32 , G06F1/3206 , G06F1/3296 , G06F1/3203
CPC classification number: G06F1/3296 , G06F1/3206 , G06F1/3203
Abstract: A management circuit is coupled to multiple processor cores for performing current suppression. The management circuit includes a detection circuit and a throttle signal generator. The detection circuit is operative to receive an activity signal from each processor core, and estimate a total current consumed by the plurality of processor cores based on activity signals. The activity signal indicates a current index proportional to current consumption of the processor core in a given time period. The throttle signal generator is operative to assert or de-assert throttle signals to the processor cores, one processor core at a time, based on one or more metrics calculated from the total current.
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公开(公告)号：US09846959B2
公开(公告)日：2017-12-19
申请号：US14642763
申请日：2015-03-10
Applicant: MEDIATEK INC.
Inventor： Ming-Hao Liao , Tsung-Liang Hou , Chin-Yuan Yao , Hung-Wei Wu
CPC classification number: G06T15/005 , G06T15/405
Abstract: A depth processing apparatus includes a depth buffer, an early depth processing circuit, a post depth processing circuit, and a depth processing controller. The depth buffer stores depth information of a plurality of pixels of a screen space. The early depth processing circuit performs early depth processing based on at least a portion of the depth information before a pixel shading stage. The post depth processing circuit performs post depth processing based on at least a portion of the depth information after the pixel shading stage. The depth processing controller manages a plurality of dependency indication values corresponding to a plurality of sub-regions in the screen space, respectively, and configured to control a first pixel for undergoing at least one of the early depth processing and the post depth processing by referring a first dependency indication value of a first sub-region in which the first pixel is located.
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Patent Agency Ranking
公开(公告)号：US09754402B2
公开(公告)日：2017-09-05
申请号：US14675759
申请日：2015-04-01
Applicant: MEDIATEK INC.
Inventor： Ming-Hao Liao , Sung-Fang Tsai , Pei-Kuei Tsung , Hung-Wei Wu
CPC classification number: G06T15/005 , G06T11/40
Abstract: A graphics processing method and an associated graphics processing apparatus, where the graphics processing method is applied to the graphics processing apparatus, the graphics processing apparatus may be positioned within an electronic device, and the graphics processing apparatus may comprise at least one portion of the electronic device. The graphics processing method includes the steps of: calculating vertex positions of a primitive in a binning phase; determining, according to specific information, whether to compute vertex varyings of the primitive in the binning phase or in a rendering phase so as to provide a determination result; computing the vertex varyings in the binning phase or in the rendering phase according to the determination result; and rendering the primitive according to the vertex positions and the vertex varyings in the rendering phase.
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公开(公告)号：US20160180579A1
公开(公告)日：2016-06-23
申请号：US14576036
申请日：2014-12-18
Applicant: MediaTek Inc.
Inventor： Ming-Hao Liao , Chih-Ching Chen , Hung-Wei Wu
CPC classification number: G06T15/405 , G06T15/005
Abstract: A depth processing method and associated graphic processing circuit is provided. The method comprises loading geometry data of a scene and performing a vertex transformation thereof. After the geometry data is segmented in a tile resolution, pre-depth data of the scene are obtained. After the geometry data are segmented in a bin resolution, plural bin tables are generated. Then, the plural bin tables are converted into plural tiles, the plural converted tiles are classified into a first portion of tiles and a second portion of tiles according to depth data of the converted tiles and the pre-depth data of the scene, and the second portion of tiles are discarded. After the first portion of tiles are processed, a color value and a depth value of each pixel of the scene are generated.
Abstract translation: 提供深度处理方法和相关的图形处理电路。 该方法包括加载场景的几何数据并执行其顶点变换。 在以瓦片分辨率分割几何数据之后，获得场景的深度数据。 在以数据分辨率分割几何数据之后，生成多个表格。 然后，将多个bin表转换成多个瓦片，根据转换瓦片的深度数据和场景的深度数据将多个转换瓦片分类为瓦片的第一部分和瓦片的第二部分，并且 瓦片的第二部分被丢弃。 在对瓷砖的第一部分进行处理之后，生成场景的每个像素的颜色值和深度值。
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8.发明申请Graphic Processing Circuit With Binning Rendering And Pre-Depth Processing Method Thereof 有权具有分层渲染和深度处理方法的图形处理电路公开(公告)号：US20160180539A1
公开(公告)日：2016-06-23
申请号：US14582134
申请日：2014-12-23
Applicant: MediaTek Inc.
Inventor： Ming-Hao Liao , Chih-Ching Chen , Shih-Chin Lin , Hung-Wei Wu
CPC classification number: G06T15/005 , G06T15/40
Abstract: A graphic processing circuit with binning rendering and associated pre-depth processing method is provided. Firstly, a first depth data of a first primitive corresponding to a specified tile is received. Then, the pre-depth data corresponding to the specified tile is read from a pre-Z buffer. If the first depth data is not larger than the pre-depth data and the first primitive is an opaque primitive, the pre-depth data is updated with the first depth data. If the first depth data is not larger than the pre-depth data and the first primitive is a translucent primitive, an uncertainty ordering range is defined according to the first depth data and the pre-depth data, and the pre-depth data is updated with the uncertainty ordering range.
Abstract translation: 提供了具有binning渲染和相关的预深度处理方法的图形处理电路。 首先，接收对应于指定瓦片的第一原语的第一深度数据。 然后，从预Z缓冲器读取对应于指定瓦片的预深度数据。 如果第一深度数据不大于预深度数据，并且第一原语是不透明原语，则用第一深度数据更新预深度数据。 如果第一深度数据不大于预深度数据，并且第一图元是半透明图元，则根据第一深度数据和预深度数据来定义不确定性排序范围，并且更新预深度数据 具有不确定性排序范围。
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9.发明申请公开(公告)号：US20160005143A1
公开(公告)日：2016-01-07
申请号：US14680081
申请日：2015-04-07
Applicant: MEDIATEK INC.
Inventor： Chun-Shen Liu , Ming-Hao Liao , Hung-Wei Wu
CPC classification number: G06T1/60 , G06T11/40 , G06T15/005 , G06T15/40
Abstract: A graphics processing system includes a decision logic and a varying buffer control circuit. The decision logic sets a control signal by checking at least one criterion, wherein the at least one criterion includes a first criterion, and a checking result of the first criterion depends on a size of a primitive. The varying buffer control circuit refers to the control signal to determine whether to store varying variables of the primitive into a varying buffer.
Abstract translation: 图形处理系统包括判定逻辑和变化的缓冲器控制电路。 所述决策逻辑通过检查至少一个标准来设置控制信号，其中所述至少一个标准包括第一准则，并且所述第一准则的检查结果取决于原语的大小。 变化的缓冲器控制电路是指控制信号，以确定是否将变化的原语变量存储到变化的缓冲器中。
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公开(公告)号：US09792722B2
公开(公告)日：2017-10-17
申请号：US14576036
申请日：2014-12-18
Applicant: MediaTek Inc.
Inventor： Ming-Hao Liao , Chih-Ching Chen , Hung-Wei Wu
CPC classification number: G06T15/405 , G06T15/005
Abstract: A depth processing method and associated graphic processing circuit is provided. The method comprises loading geometry data of a scene and performing a vertex transformation thereof. After the geometry data is segmented in a tile resolution, pre-depth data of the scene are obtained. After the geometry data are segmented in a bin resolution, plural bin tables are generated. Then, the plural bin tables are converted into plural tiles, the plural converted tiles are classified into a first portion of tiles and a second portion of tiles according to depth data of the converted tiles and the pre-depth data of the scene, and the second portion of tiles are discarded. After the first portion of tiles are processed, a color value and a depth value of each pixel of the scene are generated.
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