公开(公告)号：US20230280913A1

公开(公告)日：2023-09-07

申请号：US18078047

申请日：2022-12-08

Applicant: MEDIATEK INC.

Inventor： Yu-Hua Huang ,  Po-Chao Fang ,  Wei-Yu Ma ,  Chung-Hsin Huang

IPC: G06F3/06 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/4093

CPC classification number: G06F3/0625 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4093 ,  G06F3/0611 ,  G06F3/0673 ,  G06F3/0659

Abstract: An electronic device includes a semiconductor chip and a first memory device. The semiconductor chip includes an input/output (I/O) interface circuit. The first memory device is external to the semiconductor chip. The semiconductor chip communicates with the first memory device via the I/O interface circuit. The semiconductor chip stores at least one hardware setting of the semiconductor chip into the first memory device before a power-off event of the semiconductor chip.

公开(公告)号：US11444611B2

公开(公告)日：2022-09-13

申请号：US17474326

申请日：2021-09-14

Applicant: MEDIATEK INC.

Inventor： Wei-Yu Ma

IPC: H03K5/1252 ,  H03K3/037 ,  H03K17/687

Abstract: A hysteresis circuit to be produced within a receiver of a chip is shown. The hysteresis circuit is powered by an overdrive voltage (2VDD), and has a protection circuit, an inverter, and a latch. The input of the hysteresis circuit is coupled to the inverter through the protection circuit, to be transformed into an output, and the latch is coupled to the inverter for positive feedback control. The protection circuit has a first sub-circuit (coupling the input to the inverter to control the pull-up path of the inverter) biased by a first bias voltage that is lower than VDD, and a second sub-circuit (coupling the input to the inverter to control the pull-down path of the inverter) biased by a second bias voltage that is greater than VDD.

公开(公告)号：US10965118B2

公开(公告)日：2021-03-30

申请号：US16151355

申请日：2018-10-04

Applicant: MEDIATEK INC.

Inventor： Wei-Yu Ma

IPC: H02H7/20 ,  H03K17/082 ,  H02H9/04

Abstract: An EOS/ESD protection apparatus includes a voltage detection circuit, a controlling circuit having a switch unit, an inverter circuit, and a clamp transistor. The voltage detection circuit is configured to detect whether an over voltage event occurs in a power supply line to generate a switch control signal. The switch unit is turned on/off to generate a voltage control signal according to the switch control signal. The inverter circuit has an output and an input coupled to the voltage control signal transmitted from the controlling circuit. The clamp transistor has a control terminal coupled to the output of the inverter and is configured to be turned on when the over voltage event occurs in the power supply line.

公开(公告)号：US20190245341A1

公开(公告)日：2019-08-08

申请号：US16151355

申请日：2018-10-04

Applicant: MEDIATEK INC.

Inventor： Wei-Yu Ma

IPC: H02H7/20 ,  H02H9/04 ,  H03K17/082

CPC classification number: H02H7/20 ,  H02H9/04 ,  H03K17/0822 ,  H03K2217/0081

Abstract: An EOS/ESD protection apparatus includes a voltage detection circuit, a controlling circuit having a switch unit, an inverter circuit, and a clamp transistor. The voltage detection circuit is configured to detect whether an over voltage event occurs in a power supply line to generate a switch control signal. The switch unit is turned on/off to generate a voltage control signal according to the switch control signal. The inverter circuit has an output and an input coupled to the voltage control signal transmitted from the controlling circuit. The clamp transistor has a control terminal coupled to the output of the inverter and is configured to be turned on when the over voltage event occurs in the power supply line.