公开(公告)号：US20190051609A1

公开(公告)日：2019-02-14

申请号：US16163614

申请日：2018-10-18

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung HSU ,  Tao CHENG ,  Nan-Cheng CHEN ,  Che-Ya CHOU ,  Wen-Chou WU ,  Yen-Ju LU ,  Chih-Ming HUNG ,  Wei-Hsiu HSU

IPC: H01L23/538 ,  H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US20230253389A1

公开(公告)日：2023-08-10

申请号：US18145211

申请日：2022-12-22

Applicant: MEDIATEK INC.

Inventor： Shih-Yi SYU ,  Wen-Chou WU

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L23/49811 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L25/0657 ,  H01L23/3121 ,  H01L2225/06562 ,  H01L2225/0651 ,  H01L2225/1058

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a fan-out package and a memory package stacked on the fan-out package. The fan-out package includes a first redistribution layer (RDL) structure, a first logic die, through via (TV) interconnects, and first conductive structures. The first logic die and the first conductive structures are in contact with the first RDL structure. The TV interconnects are electrically connected to the first RDL structure. The memory package includes a first substrate, a memory die, and second conductive structures. The memory die and the second conductive structures are disposed on the first substrate. The memory die is electrically connected to the first logic die using the TV interconnects and the first RDL structure. The semiconductor package assembly further includes a second substrate electrically connected to the first logic die using the first conductive structures.

公开(公告)号：US20200381365A1

公开(公告)日：2020-12-03

申请号：US16994764

申请日：2020-08-17

Applicant: MEDIATEK Inc.

Inventor： Wen-Sung HSU ,  Tao CHENG ,  Nan-Cheng CHEN ,  Che-Ya CHOU ,  Wen-Chou WU ,  Yen-Ju LU ,  Chih-Ming HUNG ,  Wei-Hsiu HSU

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065 ,  H01L25/16 ,  H01L23/50 ,  H01L23/498 ,  H01L21/683 ,  H01Q9/04 ,  H01L23/66 ,  H01Q1/22

Abstract: A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US20180061786A1

公开(公告)日：2018-03-01

申请号：US15682908

申请日：2017-08-22

Applicant: MEDIATEK INC.

Inventor： Sheng-Mou LIN ,  Chih-Chun HSU ,  Wen-Chou WU

IPC: H01L23/66 ,  H01L25/065 ,  H01L23/64

CPC classification number: H01L23/66 ,  H01L23/552 ,  H01L23/645 ,  H01L25/0657 ,  H01L25/18 ,  H01L2223/6605 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06562 ,  H01L2225/06572

Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a package substrate. An integrated circuit (IC) die having a radio frequency (RF) circuit and a memory die are stacked over the package substrate. The memory die entirely covers a first surface portion of the package substrate to define a second surface portion of the package substrate exposed from the memory die, and the IC die partially covers the first surface portion and the second surface portion of the package substrate. The RF circuit includes a first sensitive device region corresponding to the second surface portion of the package substrate and a second sensitive device region corresponding to the first surface portion of the package substrate and offsetting a memory input/output (I/O) electrical path of the memory die, as viewed from a top-view perspective.