公开(公告)号：US20160276274A1

公开(公告)日：2016-09-22

申请号：US15168519

申请日：2016-05-31

申请人： MediaTek Inc.

发明人： Ching-Chung KO ,  Tao CHENG ,  Tien-Yueh LIU ,  Ta-Hsi CHOU ,  Peng-Cheng KAO ,  Ling-Wei KE

IPC分类号： H01L23/528 ,  H01L23/58 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00

CPC分类号： H01L23/5286 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/585 ,  H01L24/05 ,  H01L2224/05124 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/00

摘要： An integrated circuit chip includes a semiconductor substrate having thereon a plurality of inter-metal dielectric (IMD) layers and a plurality of first conductive layers embedded in respective said plurality of IMD layers, wherein said first conductive layers comprise copper; a first insulating layer overlying said plurality of IMD layers and said plurality of first conductive layers; at least a first wiring line in a second conductive layer overlying said first insulating layer, for distributing power signal or ground signal, wherein said second conductive layer comprise aluminum; and at least a second wiring line in a third conductive layer overlying said second conductive layer, for distributing power signal or ground signal.

摘要翻译： 集成电路芯片包括其上具有多个金属间电介质（IMD）层的半导体衬底和嵌入在所述多个IMD层中的多个第一导电层，其中所述第一导电层包括铜; 覆盖所述多个IMD层和所述多个第一导电层的第一绝缘层; 覆盖所述第一绝缘层的第二导电层中的至少第一布线，用于分配功率信号或接地信号，其中所述第二导电层包括铝; 以及覆盖所述第二导电层的第三导电层中的至少第二布线，用于分配电力信号或接地信号。

公开(公告)号：US20190051609A1

公开(公告)日：2019-02-14

申请号：US16163614

申请日：2018-10-18

申请人： MEDIATEK Inc.

发明人： Wen-Sung HSU ,  Tao CHENG ,  Nan-Cheng CHEN ,  Che-Ya CHOU ,  Wen-Chou WU ,  Yen-Ju LU ,  Chih-Ming HUNG ,  Wei-Hsiu HSU

IPC分类号： H01L23/538 ,  H01L25/16 ,  H01L21/48 ,  H01L21/56 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/50 ,  H01L25/065 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

摘要： A semiconductor package includes a first substrate, a first layer structure, a second layer structure and a first antenna layer. The first antenna layer is formed on at least one of the first layer structure and the second layer structure. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US20160172334A1

公开(公告)日：2016-06-16

申请号：US14736684

申请日：2015-06-11

申请人： MediaTek Inc.

发明人： Wen-Sung HSU ,  Shih-Chin LIN ,  Andrew C. CHANG ,  Tao CHENG

IPC分类号： H01L25/065 ,  H01L23/528 ,  H01L23/31 ,  H01L23/498

CPC分类号： H01L25/0657 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49827 ,  H01L23/528 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311

摘要： A chip package structure and a method for forming a chip package are provided. The chip package structure includes a first package which includes at least a semiconductor die, a dielectric structure surrounding the semiconductor die, and a plurality of conductive structures penetrating through the dielectric structure and surrounding the semiconductor die. The package structure also includes an interposer substrate over the first package and a plurality of conductive features in or over the interposer substrate. The package structure further includes a second package over the interposer substrate, and the first package electrically couples the second package through the conductive structures and the conductive features.

摘要翻译： 提供了芯片封装结构和芯片封装形成方法。 芯片封装结构包括第一封装，其包括至少半导体管芯，围绕半导体管芯的电介质结构，以及贯穿介电结构并围绕半导体管芯的多个导电结构。 所述封装结构还包括位于所述第一封装上的插入器衬底以及在所述插入器衬底中或之上的多个导电特征。 封装结构还包括在插入器基板上的第二封装，并且第一封装通过导电结构和导电特征将第二封装电耦合。

公开(公告)号：US20140097012A1

公开(公告)日：2014-04-10

申请号：US14100444

申请日：2013-12-09

申请人： MediaTek Inc.

发明人： Tao CHENG

IPC分类号： H05K1/02 ,  H01L23/495 ,  G06F17/50

CPC分类号： H05K1/025 ,  G06F17/5077 ,  H01L23/49541 ,  H01L23/64 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/19051 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A leadframe for semiconductor packages is provided. The leadframe includes a die pad, a side rail, a tie bar, and a plurality of leads. The side rail is around the die pad. The tie bar connects the die pad and the side rail. The leads extend from the side rail to close proximity to the die pad. The leads includes a first lead and a second lead being at opposite locations of the leadframe relative to a center line through the die pad. The first and second leads are substantially asymmetrical with each other relative to the center line and have different impedance values. The plurality of leads are disconnected to each other.

摘要翻译： 提供半导体封装的引线框架。 引线框架包括管芯焊盘，侧轨，连杆和多个引线。 侧轨位于管芯垫周围。 连接杆连接管芯焊盘和侧轨。 引线从侧轨延伸到靠近管芯焊盘。 引线包括第一引线和第二引线，其位于引线框架相对于通过管芯焊盘的中心线的相对位置处。 第一和第二引线相对于中心线彼此基本不对称，并具有不同的阻抗值。 多个引线彼此断开。

公开(公告)号：US20200381365A1

公开(公告)日：2020-12-03

申请号：US16994764

申请日：2020-08-17

申请人： MEDIATEK Inc.

发明人： Wen-Sung HSU ,  Tao CHENG ,  Nan-Cheng CHEN ,  Che-Ya CHOU ,  Wen-Chou WU ,  Yen-Ju LU ,  Chih-Ming HUNG ,  Wei-Hsiu HSU

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065 ,  H01L25/16 ,  H01L23/50 ,  H01L23/498 ,  H01L21/683 ,  H01Q9/04 ,  H01L23/66 ,  H01Q1/22

摘要： A semiconductor package includes a first substrate, a first layer structure, a second layer structure, a first antenna layer and an electronic component. The first antenna layer is formed on at least one of the first layer structure and the second layer structure, wherein the first antenna layer has an upper surface flush with a layer upper surface of the first layer structure or the second layer structure. The electronic component is disposed on a substrate lower surface of the first substrate and exposed from the first substrate. The first layer structure is formed between the first substrate and the second layer structure.

公开(公告)号：US20160153922A1

公开(公告)日：2016-06-02

申请号：US14951698

申请日：2015-11-25

申请人： MediaTek Inc.

发明人： Yu-Min LEE ,  Chi-Wen PAN ,  Hung-Wen CHIOU ,  Tai-Yu CHEN ,  Tao CHENG ,  Wen-Sung HSU ,  Sheng-Liang LI

IPC分类号： G01N25/18

CPC分类号： G01N25/18 ,  G01N2033/0078 ,  G01N2033/0095 ,  G06F17/5009 ,  G06F2217/16

摘要： A computer system and a method for adaptive thermal resistance-capacitance (RC) network analysis of a semiconductor device for use in a portable device are provided. The method includes the steps of: receiving a device input file and a plurality of specific effective heat transfer coefficients (HTCs) associated with the portable device; repeatedly performing a thermal analysis of the portable device based on the device input file and a current effective HTC to estimate a target die temperature of the semiconductor device; calculating a target effective HTC based on the device input file and the target die temperature; and updating the current effective HTC with the target effective HTC; and generating an output file recording the target die temperature of the semiconductor device.

摘要翻译： 提供了一种用于便携式设备的半导体器件的计算机系统和用于自适应热电阻 - 电容（RC）网络分析的方法。 该方法包括以下步骤：接收与便携式设备相关联的设备输入文件和多个特定有效传热系数（HTC）; 基于设备输入文件和当前有效HTC重复执行便携式设备的热分析以估计半导体器件的目标管芯温度; 基于设备输入文件和目标模具温度计算目标有效HTC; 并用目标有效HTC更新当前有效的HTC; 以及生成记录半导体器件的目标管芯温度的输出文件。