-
公开(公告)号:US12177325B2
公开(公告)日:2024-12-24
申请号:US18523991
申请日:2023-11-30
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Dotan David Levi , Ariel Shahar , Shahaf Shuler , Ariel Almog , Eitan Hirshberg , Natan Manevich
IPC: H04L7/00
Abstract: A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.
-
公开(公告)号:US20220006606A1
公开(公告)日:2022-01-06
申请号:US17335122
申请日:2021-06-01
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Dotan David Levi , Ariel Shahar , Shahaf Shuler , Ariel Almog , Eitan Hirshberg , Natan Manevich
IPC: H04L7/00
Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.
-
公开(公告)号:US11876885B2
公开(公告)日:2024-01-16
申请号:US17335122
申请日:2021-06-01
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Dotan David Levi , Ariel Shahar , Shahaf Shuler , Ariel Almog , Eitan Hirshberg , Natan Manevich
IPC: H04L7/00
CPC classification number: H04L7/0091
Abstract: A timing system including timing circuitry which includes an arming queue, a clock work queue, and a clock completion queue. At least the clock work queue is to provide timing information, and the arming queue is to arm the clock work queue. Related apparatus and methods are also provided.
-
4.
公开(公告)号:US20200167192A1
公开(公告)日:2020-05-28
申请号:US16202132
申请日:2018-11-28
Applicant: Mellanox Technologies, Ltd.
Inventor: Eitan Hirshberg , Ariel Shahar , Najeeb Darawshy , Omri Kahalon
Abstract: A computer system includes one or more processors, one or more hardware accelerators, and control circuitry. The processors are configured to run software that executes tasks in a normal mode. The accelerators are configured to execute the tasks in an accelerated mode. The control circuitry is configured to receive one or more flows of tasks for execution by the processors and the accelerators, assign one or more initial tasks of each flow for execution by the processors, assign subsequent tasks of each flow for execution by the accelerators, and verify, for each flow, that the accelerators do not execute the subsequent tasks of the flow until the processors have fully executed the initial tasks of the flow.
-
公开(公告)号:US09462047B2
公开(公告)日:2016-10-04
申请号:US14637414
申请日:2015-03-04
Applicant: Mellanox Technologies Ltd.
Inventor: Noam Bloch , Eitan Hirshberg , Michael Kagan , Lior Narkis
IPC: H04L12/28 , H04L29/08 , H04L12/715 , H04L12/46 , G06F9/455
CPC classification number: H04L67/10 , G06F9/45533 , H04L12/4633 , H04L45/64
Abstract: A network interface device includes a host interface for connection to a host processor having a memory. A network interface is configured to transmit and receive data packets over a data network, which supports multiple tenant networks overlaid on the data network. Processing circuitry is configured to receive, via the host interface, a work item submitted by a virtual machine running on the host processor, and to identify, responsively to the work item, a tenant network over which the virtual machine is authorized to communicate, wherein the work item specifies a message to be sent to a tenant destination address. The processing circuitry generates, in response to the work item, a data packet containing an encapsulation header that is associated with the tenant network, and to transmit the data packet over the data network to at least one data network address corresponding to the specified tenant destination address.
-
公开(公告)号:US20140122556A1
公开(公告)日:2014-05-01
申请号:US13664428
申请日:2012-10-31
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor: Eitan Hirshberg
IPC: G06F7/535
CPC classification number: G06F7/535 , G06F2207/5355
Abstract: A method includes receiving a dividend and a divisor for performing a division operation. Numbers p and n are found, for which the divisor equals 2n(1+2p). An interim result, which is equal to a reciprocal of 1+2p multiplied by the dividend, is calculated. The interim result is divided by 2n to produce a result of the division operation.
Abstract translation: 一种方法包括接收用于执行除法运算的除数和除数。 数字p和n被找到,除数等于2n(1 + 2p)。 计算等于1 + 2p的乘数乘以除数的中间结果。 中间结果除以2n以产生除法运算的结果。
-
公开(公告)号:US20250080315A1
公开(公告)日:2025-03-06
申请号:US18950255
申请日:2024-11-18
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Dotan David Levi , Ariel Shahar , Shahaf Shuler , Ariel Almog , Eitan Hirshberg , Natan Manevich
IPC: H04L7/00
Abstract: A communication system includes at least one send queue, containing send queue entries pointing to packets to be transmitted over a network by packet sending circuitry. A clock work queue contains clock queue entries to synchronize sending times of the packets pointed to by the send queue entries. At least one arming queue contains arming queue entries to arm the clock work queue at selected time intervals.
-
公开(公告)号:US20150180959A1
公开(公告)日:2015-06-25
申请号:US14637414
申请日:2015-03-04
Applicant: Mellanox Technologies Ltd.
Inventor: Noam Bloch , Eitan Hirshberg , Michael Kagan , Lior Narkis
CPC classification number: H04L67/10 , G06F9/45533 , H04L12/4633 , H04L45/64
Abstract: A network interface device includes a host interface for connection to a host processor having a memory. A network interface is configured to transmit and receive data packets over a data network, which supports multiple tenant networks overlaid on the data network. Processing circuitry is configured to receive, via the host interface, a work item submitted by a virtual machine running on the host processor, and to identify, responsively to the work item, a tenant network over which the virtual machine is authorized to communicate, wherein the work item specifies a message to be sent to a tenant destination address. The processing circuitry generates, in response to the work item, a data packet containing an encapsulation header that is associated with the tenant network, and to transmit the data packet over the data network to at least one data network address corresponding to the specified tenant destination address.
-
9.
公开(公告)号:US09008097B2
公开(公告)日:2015-04-14
申请号:US13731130
申请日:2012-12-31
Applicant: Mellanox Technologies Ltd.
Inventor: Noam Bloch , Eitan Hirshberg , Michael Kagan
IPC: H04L12/28 , H04L12/715
CPC classification number: H04L67/10 , G06F9/45533 , H04L12/4633 , H04L45/64
Abstract: A network interface device includes a host interface for connection to a host processor having a memory. A network interface is configured to transmit and receive data packets over a data network, which supports multiple tenant networks overlaid on the data network. Processing circuitry is configured to receive, via the host interface, a work item submitted by a virtual machine running on the host processor, and to identify, responsively to the work item, a tenant network over which the virtual machine is authorized to communicate, wherein the work item specifies a message to be sent to a tenant destination address. The processing circuitry generates, in response to the work item, a data packet containing an encapsulation header that is associated with the tenant network, and to transmit the data packet over the data network to at least one data network address corresponding to the specified tenant destination address.
Abstract translation: 网络接口设备包括用于连接到具有存储器的主机处理器的主机接口。 网络接口被配置为通过数据网络发送和接收数据分组,数据网络支持覆盖在数据网络上的多个租户网络。 处理电路被配置为经由主机接口接收由主机处理器上运行的虚拟机提交的工作项,并且响应于工作项识别虚拟机被授权通信的租户网络,其中 工作项目指定要发送到租户目标地址的消息。 处理电路响应于工作项产生包含与租户网络相关联的封装头部的数据分组,并且通过数据网络将数据分组发送到与指定的租户目的地对应的至少一个数据网络地址 地址。
-
10.
公开(公告)号:US20140185616A1
公开(公告)日:2014-07-03
申请号:US13731130
申请日:2012-12-31
Applicant: MELLANOX TECHNOLOGIES LTD.
Inventor: Noam Bloch , Eitan Hirshberg , Michael Kagan
IPC: H04L12/56
CPC classification number: H04L67/10 , G06F9/45533 , H04L12/4633 , H04L45/64
Abstract: A network interface device includes a host interface for connection to a host processor having a memory. A network interface is configured to transmit and receive data packets over a data network, which supports multiple tenant networks overlaid on the data network. Processing circuitry is configured to receive, via the host interface, a work item submitted by a virtual machine running on the host processor, and to identify, responsively to the work item, a tenant network over which the virtual machine is authorized to communicate, wherein the work item specifies a message to be sent to a tenant destination address. The processing circuitry generates, in response to the work item, a data packet containing an encapsulation header that is associated with the tenant network, and to transmit the data packet over the data network to at least one data network address corresponding to the specified tenant destination address.
Abstract translation: 网络接口设备包括用于连接到具有存储器的主机处理器的主机接口。 网络接口被配置为通过数据网络发送和接收数据分组,数据网络支持覆盖在数据网络上的多个租户网络。 处理电路被配置为经由主机接口接收由主机处理器上运行的虚拟机提交的工作项,并且响应于工作项识别虚拟机被授权通信的租户网络,其中 工作项目指定要发送到租户目标地址的消息。 处理电路响应于工作项产生包含与租户网络相关联的封装头部的数据分组,并且通过数据网络将数据分组发送到与指定的租户目的地对应的至少一个数据网络地址 地址。
-
-
-
-
-
-
-
-
-