公开(公告)号：US20230229196A1

公开(公告)日：2023-07-20

申请号：US17924526

申请日：2021-05-12

申请人： MIANYANG BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

发明人： Ming Li ,  Lin Xiong ,  Yuliang Wang ,  Jun Wang ,  Xu Zhao ,  Shenghua Bai ,  Jie Li ,  Xing Zou ,  Fanyou Li ,  Mu Zeng ,  Chao Liu ,  Miao Wang ,  Jie Tu ,  Zhoujun Chen ,  Guifang He ,  Chunrong Lai

IPC分类号： G06F1/16

CPC分类号： G06F1/1656 ,  G06F1/1616

摘要： The display module (100) includes: a supporting member (2) and a display panel (2), supporting member (1) includes an interlayer part (11) and a supporting part (12), the surface of the side of the supporting part (12) that is away from the interlayer part (11) is a supporting curved face (121), the supporting curved face (121) protrudes in the direction away from the interlayer part (11), the display panel (2) includes a non-bending part (21), a bending part (22) and a connecting part (23), the non-bending part (21) and the connecting part (23) are located on the two sides of the interlayer part (11) in the thickness direction of the interlayer part (11), the bending part (22) supports the side of the supporting part (12) that is away from the interlayer part (11), and the inner surface of the bending part (22) adheres to the supporting curved face (121).

公开(公告)号：US09893206B2

公开(公告)日：2018-02-13

申请号：US15146643

申请日：2016-05-04

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Yuliang Wang ,  Daeyoung Choi ,  Zengli Liu ,  Daojie Li ,  Fei Al ,  Jun Zhou

IPC分类号： H01L29/10 ,  H01L29/786 ,  H01L29/66 ,  H01L29/45 ,  H01L21/3213

CPC分类号： H01L29/78696 ,  H01L21/32134 ,  H01L29/458 ,  H01L29/66765 ,  H01L29/78669

摘要： The present disclosure provides a TFT, an array substrate, their manufacturing methods, and a display device. A source electrode and a drain electrode of the TFT are each of a multi-layered structure including a metal layer and a metal barrier layer. An a-Si active layer of the TFT is covered with an etch stop layer, via-holes penetrating through the etch stop layer are provided at positions corresponding to the source electrode and the drain, and the source electrode and the drain electrode are connected to the a-Si active layer through the via-holes.

公开(公告)号：US09698178B2

公开(公告)日：2017-07-04

申请号：US14897525

申请日：2015-04-30

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Yuliang Wang ,  Daeyoung Choi ,  Zengli Liu ,  Daojie Li ,  Shijuan Chen

IPC分类号： H01L27/12 ,  H01L21/786 ,  H01L21/84 ,  H01L21/027 ,  H01L21/4757 ,  H01L21/768 ,  H01L29/66 ,  H01L29/786

CPC分类号： H01L27/1288 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/47573 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/84 ,  H01L27/12 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/66969 ,  H01L29/7869

摘要： A method for manufacturing an array substrate includes coating a photoresist onto an insulation layer including a gate insulation layer and an etch stop layer, wherein the gate insulation layer covers a conductive pattern and the etch stop layer covers a semiconductive pattern. The method further includes exposing the photoresist to form a photoresist partially-reserved region and a photoresist unreserved region. The method further includes performing a first etching process to at least partially remove a portion of the insulation layer located at a position corresponding to the photoresist unreserved region, to form an intermediate hole. The method further includes performing a second etching process to form the first via hole and form the second via hole at a position of the intermediate hole, thereby to reveal the semiconductive pattern and the conductive pattern at positions corresponding to the first via hole and the second via hole, respectively.