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    Virtual General Purpose Input/Output For A Microcontroller
    2.
    发明申请
    Virtual General Purpose Input/Output For A Microcontroller 审中-公开

    公开(公告)号：US20180181526A1

    公开(公告)日：2018-06-28

    申请号：US15901222

    申请日：2018-02-21

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Simmons

    IPC: G06F13/40

    CPC classification number: G06F13/4068

    Abstract: A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.

    Security of embedded devices through a device lifecycle with a device identifier
    4.
    发明授权
    Security of embedded devices through a device lifecycle with a device identifier 有权

    公开(公告)号：US11663146B2

    公开(公告)日：2023-05-30

    申请号：US16806227

    申请日：2020-03-02

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Simmons

    IPC: G06F12/14 ,  G06F3/06

    CPC classification number: G06F12/1416 ,  G06F3/0616 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

    Abstract: An apparatus includes a database with device profiles, and a device programmer. The device programmer includes instructions. The instructions, when read and executed by a processor, cause the device programmer to identify a device identifier of an electronic device. The device programmer is further caused to, based upon the device identifier, access device data from the database. The device programmer is further caused to, based upon the device data, determine an area of memory of the electronic device that can be written. The device programmer is further caused to, based on the determination of the area of memory of the electronic device that can be written, write data to the area of memory.

    Memory pool allocation for a multi-core system
    5.
    发明授权
    Memory pool allocation for a multi-core system 有权

    公开(公告)号：US11461139B2

    公开(公告)日：2022-10-04

    申请号：US16842870

    申请日：2020-04-08

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Simmons ,  Anjana Priya Sistla ,  Priyank Gupta

    IPC: G06F9/50 ,  G06F8/41 ,  G06F9/54 ,  G06F12/02

    Abstract: An apparatus includes processing cores, memory blocks, a connection between each of processing core and memory block, chip selection circuit, and chip selection circuit busses between the chip selection circuit and each of the memory blocks. Each memory block includes a data port and a memory check port. The chip selection circuit is configured to enable writing data from a highest priority core through respective data ports of the memory blocks. The chip selection circuit is further configured to enable writing data from other cores through respective memory check ports of the memory blocks.

    One Time Programmable Memory
    6.
    发明申请
    One Time Programmable Memory 审中-公开
    一次性可编程存储器

    公开(公告)号：US20160276042A1

    公开(公告)日：2016-09-22

    申请号：US15072759

    申请日：2016-03-17

    Applicant: Microchip Technology Incorporated

    Inventor： Rodney Pesavento ,  Michael Simmons

    IPC: G11C17/16 ,  G11C29/00

    Abstract: Systems and method for controlling the programming of a one-time programmable (OTP) memory are disclosed. The systems and methods include an OTP memory array comprising an array organized in lines of n+1 bit, wherein n is an integer number designating a word size of the OTP memory, wherein the additional bit indicates whether a memory line is stored in an inverted or non-inverted fashion, encoding logic configured determine whether a word is to be stored inverted or non-inverted, and decoding logic configured to decode a stored word and controlled by the additional bit indicating whether a word has been stored inverted or non-inverted.

    Abstract translation: 公开了一种用于控制一次性可编程（OTP）存储器的编程的系统和方法。 该系统和方法包括一个OTP存储器阵列，其包括以n + 1位行的方式组织的阵列，其中n是指定OTP存储器的字大小的整数，其中附加位指示存储器线是否以倒置 或非反转方式，配置的编码逻辑确定字是否被反转或非反相存储，以及解码逻辑，其被配置为对存储的字进行解码并由附加位控制，指示字是否已被反转或非反相存储 。

    Security of embedded devices through a device lifecycle with a device identifier
    7.
    发明授权
    Security of embedded devices through a device lifecycle with a device identifier 有权

    公开(公告)号：US12117941B2

    公开(公告)日：2024-10-15

    申请号：US18136446

    申请日：2023-04-19

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Simmons

    IPC: G06F12/14 ,  G06F3/06

    CPC classification number: G06F12/1416 ,  G06F3/0616 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679

    Abstract: An apparatus includes a database with device profiles, and a device programmer. The device programmer includes instructions. The instructions, when read and executed by a processor, cause the device programmer to identify a device identifier of an electronic device. The device programmer is further caused to, based upon the device identifier, access device data from the database. The device programmer is further caused to, based upon the device data, determine an area of memory of the electronic device that can be written. The device programmer is further caused to, based on the determination of the area of memory of the electronic device that can be written, write data to the area of memory.

    Interfacing with systems, for processing data samples, and related systems, methods and apparatuses
    8.
    发明授权
    Interfacing with systems, for processing data samples, and related systems, methods and apparatuses 有权

    公开(公告)号：US11698872B2

    公开(公告)日：2023-07-11

    申请号：US17457185

    申请日：2021-12-01

    Applicant: Microchip Technology Incorporated

    Inventor： Narendra Raj S V ,  Priyank Gupta ,  Michael Simmons

    IPC: G06F13/16 ,  G06F3/06 ,  G06F5/06 ,  G06F13/28

    CPC classification number: G06F13/1673 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0647 ,  G06F3/0679 ,  G06F5/06 ,  G06F13/28

    Abstract: Disclosed examples include an apparatus. The apparatus may include first interfaces, second interfaces, a bus interface, and a buffer interface. The first interfaces may be to communicate at first data widths via first interconnects for operable coupling with data samples sources. The second interface may be to communicate at second data widths via second interconnects for operable coupling with data sinks. The buffer interface may be to communicate with a system to process data samples sampled using different sampling rates according to processing frame durations. The buffer interface may include an uplink channel handler and a downlink channel handler. The uplink channel handler may be to receive data samples from the first interfaces at first data widths and provide the data samples to the bus interface at third data widths. The downlink channel handler may be to receive processed data samples from the bus interface at third data widths and provide the processed data samples to the second interfaces at second data widths. The bus interface to communicate at a third data width via a third interconnect for operative coupling with allocated memory region utilized by the system to process data samples.

    Memory Pool Allocation for a Multi-Core System
    10.
    发明申请
    Memory Pool Allocation for a Multi-Core System 审中-公开

    公开(公告)号：US20200233714A1

    公开(公告)日：2020-07-23

    申请号：US16842870

    申请日：2020-04-08

    Applicant: Microchip Technology Incorporated

    Inventor： Michael Simmons ,  Anjana Priya Sistla ,  Priyank Gupta

    IPC: G06F9/50 ,  G06F8/41 ,  G06F9/54 ,  G06F12/02

    Abstract: An apparatus includes processing cores, memory blocks, a connection between each of processing core and memory block, chip selection circuit, and chip selection circuit busses between the chip selection circuit and each of the memory blocks. Each memory block includes a data port and a memory check port. The chip selection circuit is configured to enable writing data from a highest priority core through respective data ports of the memory blocks. The chip selection circuit is further configured to enable writing data from other cores through respective memory check ports of the memory blocks.

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