公开(公告)号：US20240160359A1

公开(公告)日：2024-05-16

申请号：US18419895

申请日：2024-01-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Jonathan S. Parry ,  Nicola Ciocchini ,  Animesh Roy Chowdhury ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo’ Righetti ,  Ugo Russo

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The processing device is further to receive a second read command at a second time. The processing device is further to determine that the first read command and the second read command are directed to an at least partially same set of memory cells of the plurality of memory cells. The processing device is further to perform a media management operation with respect to the at least partially same set of memory cells.

公开(公告)号：US20240161838A1

公开(公告)日：2024-05-16

申请号：US18505855

申请日：2023-11-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nicola Ciocchini ,  Animesh Roy Chowdhury ,  Kishore Kumar Muchherla ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo’ Righetti ,  Jonathan S. Parry ,  Ugo Russo

IPC: G11C16/34 ,  G11C7/04 ,  G11C16/32

CPC classification number: G11C16/3431 ,  G11C7/04 ,  G11C16/32

Abstract: A system may include a memory device comprising a plurality of memory blocks, and a processing device to, responsive to receiving a request to read a memory block from the memory device, determine a time difference between a current time and a timestamp associated with the memory block, determine whether the time difference satisfies a first threshold increment criterion, responsive to determining that the time difference satisfies the first threshold increment criterion, increment a read counter associated with the memory block by a first increment value associated with the first threshold increment criterion, determine that the read counter associated with the memory block satisfies a threshold scan criterion, and responsive to determining that the read counter satisfies the threshold scan criterion, perform a media scan with respect to the memory block.

公开(公告)号：US11922029B2

公开(公告)日：2024-03-05

申请号：US17863000

申请日：2022-07-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Jonathan S. Parry ,  Nicola Ciocchini ,  Animesh Roy Chowdhury ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo' Righetti ,  Ugo Russo

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.

公开(公告)号：US20230393756A1

公开(公告)日：2023-12-07

申请号：US17863000

申请日：2022-07-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Jonathan S. Parry ,  Nicola Ciocchini ,  Animesh Roy Chowdhury ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo' Righetti ,  Ugo Russo

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0653

Abstract: A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.