公开(公告)号：US20240296892A1

公开(公告)日：2024-09-05

申请号：US18659845

申请日：2024-05-09

Applicant: Micron Technology, Inc.

Inventor： Zhongyuan Lu ,  Niccolo' Righetti

IPC: G11C16/16 ,  G11C7/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32

CPC classification number: G11C16/16 ,  G11C7/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32

Abstract: Bake temperatures for memory blocks can be determined as part of an operation to allocate memory blocks for us by a memory device. If a temperature of a particular memory block among the plurality of memory blocks meets or exceeds a threshold operational temperature corresponding to a memory device containing the plurality of memory blocks, the particular memory block can be allocated for receipt and/or storage of data.

公开(公告)号：US20240168880A1

公开(公告)日：2024-05-23

申请号：US18386783

申请日：2023-11-03

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Niccolo' Righetti ,  Shyam Sunder Raghunathan ,  Leo Raimondo ,  Kishore K. Muccherla

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: An apparatus can comprise a memory array comprising multiple erase blocks coupled to a same plurality of strings of memory cells. A controller is configured to monitor a cumulative amount of read disturb stress experienced by a first erase block by: maintaining a read disturb count corresponding to the first erase block; incrementing the read disturb count by a first amount responsive to read commands issued to addresses corresponding to the first erase block; incrementing the read disturb count by a read disturb scaling factor responsive to read commands issued to addresses corresponding to the second erase block; and incrementing the read disturb count by a program scaling factor responsive to program commands issued to addresses corresponding to the second erase block. The controller can perform an action on the first erase block responsive to the read disturb count exceeding a threshold value.

公开(公告)号：US20240126448A1

公开(公告)日：2024-04-18

申请号：US17967265

申请日：2022-10-17

Applicant: Micron Technology, Inc.

Inventor： Animesh R. Chowdhury ,  Kishore K. Muchherla ,  Nicola Ciocchini ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo' Righetti ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: Apparatuses, systems, and methods for adapting a read disturb scan. One example method can include determining a delay between a first read command and a second read command, incrementing a read count based on the determined delay between the first read command and the second read command, and adapting a read disturb scan rate based on the incremented read count.

公开(公告)号：US11847335B2

公开(公告)日：2023-12-19

申请号：US17212437

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Scott Anthony Stoller ,  Niccolo' Righetti ,  Giuseppina Puzzilli

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/0679

Abstract: A trigger condition associated with latent read disturb in a memory device is detected. In response to detecting the trigger condition associated with latent read disturb, one or more blocks in the memory device that are impacted by the trigger condition are placed in a stable state to mitigate latent read disturb in the one or more blocks.

公开(公告)号：US11776629B2

公开(公告)日：2023-10-03

申请号：US16995517

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Niccolo' Righetti ,  Kishore K. Muchherla ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G11C16/10 ,  G11C16/14

CPC classification number: G11C16/10 ,  G11C16/14

Abstract: A method includes during a first portion of a service life of a memory device, programming at least one memory cell of the memory device to a first threshold voltage corresponding to a desired data state. The method can include during a second portion of the service life of the memory device subsequent to the first portion of the service life of the memory device, programming at least one memory cell of the memory device to a second threshold voltage corresponding to the desired data state. The second threshold voltage can be different than the first threshold voltage.

公开(公告)号：US20230214133A1

公开(公告)日：2023-07-06

申请号：US18090449

申请日：2022-12-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kishore Kumar Muchherla ,  Akira Goda ,  Jeffrey S. McNeil ,  Niccolo' Righetti ,  Silvia Beltrami ,  Violante Moschiano ,  Ugo Russo

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0659

Abstract: A memory device comprises an array of memory cells organized into a plurality of wordlines, and a processing device to perform processing operations that receive a program command specifying a memory unit and data comprising first received data, where the plurality of wordlines includes one or more first active data wordlines and a group of consecutive retired wordlines. The processing operations also program the specified data to the memory unit by programming the first received data to the one or more first active data wordlines, identifying a first retired boundary wordline that is in the group of consecutive retired wordlines and is adjacent to one of the first active data wordlines, generating a first data pattern comprising a first plurality of threshold voltage levels, and programming the first data pattern to the first retired boundary wordline.

公开(公告)号：US20220197536A1

公开(公告)日：2022-06-23

申请号：US17127373

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Priya Venkataraman ,  Pitamber Shukla ,  Scott A. Stoller ,  Giuseppina Puzzilli ,  Niccolo' Righetti

IPC: G06F3/06

Abstract: A method is described that includes determining a number of program and erase cycles associated with a block of pages of a memory device and determining a preprogram voltage based on the number of program and erase cycles to apply to the block of pages prior to an erase operation. The method further includes applying the preprogram voltage to the block of pages and performing an erase operation on the block of pages following application of the preprogram voltage to the block of pages.

公开(公告)号：US20250053301A1

公开(公告)日：2025-02-13

申请号：US18929570

申请日：2024-10-28

Applicant: Micron Technology, Inc,

Inventor： Jeffrey S. McNeil ,  Jonathan S. Parry ,  Ugo Russo ,  Akira Goda ,  Kishore Kumar Muchherla ,  Violante Moschiano ,  Niccolo' Righetti ,  Silvia Beltrami

IPC: G06F3/06

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

公开(公告)号：US20240145010A1

公开(公告)日：2024-05-02

申请号：US18404827

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Nicola Ciocchini ,  Zhenlei Shen ,  Charles See Yeung Kwong ,  Murong Lang ,  Ugo Russo ,  Niccolo' Righetti

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3481

Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.

公开(公告)号：US11694763B2

公开(公告)日：2023-07-04

申请号：US17700085

申请日：2022-03-21

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G11C29/44 ,  G11C29/42 ,  G06F11/30 ,  G06F11/07 ,  G11C29/12

CPC classification number: G11C29/44 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/3037 ,  G11C29/12005 ,  G11C29/42

Abstract: A system includes a memory device having a plurality of groups of memory cells and a processing device communicatively coupled to the memory device. The processing device is be configured to read a first group of memory cells of the plurality to determine a calibrated read voltage associated with the group of memory cells. The processing device is further configured to determine, using the calibrated read voltage associated with the first group of memory cells, a bit error rate (BER) of a second group of memory cells of the plurality. Prior to causing the memory device to perform a copyback operation on the plurality of groups of memory cells, the processing device is further configured to determine whether to perform a subsequent read voltage calibration on at least the second group of the plurality based, at least partially, on a comparison between the determined BER and a threshold BER.