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    BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTION DECODER THROUGHPUT SPECIFICATIONS
    3.
    发明公开
    BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTION DECODER THROUGHPUT SPECIFICATIONS 审中-公开

    公开(公告)号：US20240071547A1

    公开(公告)日：2024-02-29

    申请号：US18231514

    申请日：2023-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Guang Hu ,  Nicola Ciocchini

    IPC: G11C29/32

    CPC classification number: G11C29/32

    Abstract: A memory device includes a memory array and control logic operatively coupled with the memory array to perform operations including maintaining a set of bins, each bin of the set of bins defining a respective grouping of memory arrays based on elapsed time since programming, wherein each bin of the set of bins is assigned a respective read level offset to achieve a bit error rate satisfying a threshold condition for an error correction decoder throughput specification, receiving a request to perform a read operation addressing the memory array, and causing the read operation to be performed based on the set of bins.

    APPARATUSES AND METHODS FOR ACCESSING VARIABLE RESISTANCE MEMORY DEVICE
    5.
    发明申请
    APPARATUSES AND METHODS FOR ACCESSING VARIABLE RESISTANCE MEMORY DEVICE 有权
    用于访问可变电阻存储器件的装置和方法

    公开(公告)号：US20160133319A1

    公开(公告)日：2016-05-12

    申请号：US14535099

    申请日：2014-11-06

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Paolo Fantini ,  Daniele Ielmini ,  Nicola Ciocchini

    IPC: G11C13/00

    CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0092 ,  G11C2213/76

    Abstract: The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to a memory device having a controller configured to cause a write operation to be performed on a variable resistance memory cell, which includes application of two successive access pulses having opposite polarities, and methods of using the same.

    Abstract translation: 所公开的技术通常涉及其操作的存储装置和方法，更具体地涉及一种存储器件，其具有被配置为对可变电阻存储单元执行写操作的控制器，该控制器包括应用两个连续存取脉冲， 相反的极性，以及使用它们的方法。

    DYNAMICALLY BOOSTING READ VOLTAGE FOR A MEMORY DEVICE
    9.
    发明申请
    DYNAMICALLY BOOSTING READ VOLTAGE FOR A MEMORY DEVICE 有权

    公开(公告)号：US20220165333A1

    公开(公告)日：2022-05-26

    申请号：US17101846

    申请日：2020-11-23

    Applicant: Micron Technology, Inc.

    Inventor： Nicola Ciocchini ,  Andrea Gotti

    IPC: G11C13/00 ,  H01L45/00

    Abstract: Systems, methods, and apparatus related to dynamically determining read voltages used in memory devices. In one approach, a memory device has a memory array including memory cells. One or more resistors are formed as part of the memory array. A memory controller increments a counter as write operations are performed on the memory cells. When the counter reaches a limit, a write operation is performed on the resistors. The write operation applies voltages to the resistors similarly as applied to the memory cells over time during normal operation. When performing a read operation, a current is applied to one or more of the resistors to determine a boost voltage. When reading the memory cells, a read voltage is adjusted based on the boost voltage. The memory cells are read using the adjusted read voltage.

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