公开(公告)号：US20250118344A1

公开(公告)日：2025-04-10

申请号：US18774431

申请日：2024-07-16

Applicant: Micron Technology, Inc.

Inventor： Stephen Hanna ,  Jonathan S. Parry

IPC: G11C7/10 ,  G11C29/52

Abstract: Methods, systems, and devices for serial pass-through techniques for memory device interfaces are described. Memory interface circuitry may be configured to receive a command via a first interface having a first set of terminals to configure the memory interface circuitry for a pass-through mode. As part of the pass-through mode, the memory interface circuitry may receive data from an external device via the first interface and output the data to one or more memory devices via a second interface having a second set of terminals. In some examples, the received data may be associated with a write burst, in which the memory interface circuitry may serially receive multiple portions of the data to write to a buffer of the memory interface circuitry. After reaching a threshold quantity of data, the buffer may output the portions of the data to the one or more memory devices via the second interface.

公开(公告)号：US12235707B2

公开(公告)日：2025-02-25

申请号：US17578273

申请日：2022-01-18

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Stephen L. Miller ,  Liang Yu

IPC: G06F1/3225 ,  G06F1/26 ,  G06F1/3212 ,  G06F1/3234 ,  G11C5/14 ,  G11C11/4074 ,  H01L23/00

Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides for converting each respective signal to a respective analog voltage to drive a common node; and utilizing a charge storage device coupled to the common node to accumulate the respective analog voltages from the dice, where the accumulated voltage indicates total power consumption of the dice.

公开(公告)号：US20250014655A1

公开(公告)日：2025-01-09

申请号：US18895236

申请日：2024-09-24

Applicant: Micron Technology, Inc.

Inventor： Nicola Ciocchini ,  Animesh R. Chowdhury ,  Kishore Kumar Muchherla ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo' Righetti ,  Jonathan S. Parry

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/26

Abstract: Methods, systems, and apparatuses include receiving a read command including a logical address. The read command is directed to a portion of memory composed of blocks and each block is composed of wordline groups. The physical address for the read command is identified using the logical address. The wordline group is determined using the physical address. A slope factor is retrieved using the wordline group. A read counter is incremented using the slope factor.

公开(公告)号：US12131028B2

公开(公告)日：2024-10-29

申请号：US18121494

申请日：2023-03-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jeffrey S. McNeil ,  Jonathan S. Parry ,  Ugo Russo ,  Akira Goda ,  Kishore Kumar Muchherla ,  Violante Moschiano ,  Niccolo' Righetti ,  Silvia Beltrami

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679

Abstract: Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.

公开(公告)号：US20240345750A1

公开(公告)日：2024-10-17

申请号：US18638471

申请日：2024-04-17

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Jonathan S. Parry

IPC: G06F3/06 ,  G06F1/3234 ,  G06F1/3296

CPC classification number: G06F3/0634 ,  G06F1/3275 ,  G06F1/3296 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673

Abstract: Methods, systems, and devices for host recovery for a stuck condition of a memory system are described. The host system may transmit a first command for the memory system to transition from a first power mode to a second power mode (e.g., low-power mode). In some cases, the host system may transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system may activate a timer associated with a time-out condition for exiting the second power mode and may determine that a duration indicated by the timer expires. In some examples, the host system may transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.

公开(公告)号：US20240330519A1

公开(公告)日：2024-10-03

申请号：US18624775

申请日：2024-04-02

Applicant: Micron Technology, Inc.

Inventor： Christian M. Gyllenskog ,  Jonathan S. Parry

IPC: G06F21/79 ,  G06F12/02 ,  G06F21/10 ,  G06F21/54 ,  G06F21/60

CPC classification number: G06F21/79 ,  G06F12/0246 ,  G06F12/0253 ,  G06F21/54 ,  G06F21/602 ,  G06F21/107

Abstract: Methods, systems, and devices for purging data from a memory device are described. A memory system may receive, from a host system, a command to write data to an address storing an encryption key in a first portion of the memory system that is configured to store secure information (e.g., a Replay Protected Memory Block). The encryption key may be configured to encrypt data associated with the host system that is stored in a second portion of the memory system. The memory system may then receive an indication of a purge command from the host system. The memory system may execute the purge command by transferring data from the first portion of the memory system to a third portion of the memory system configured to store secure information and erasing the data from the first portion of the memory system.

公开(公告)号：US20240329721A1

公开(公告)日：2024-10-03

申请号：US18597462

申请日：2024-03-06

Applicant: Micron Technology, Inc.

Inventor： Deping He ,  Nadav Grosz ,  Jonathan S. Parry

IPC: G06F1/3234 ,  G06F1/3287

CPC classification number: G06F1/3275 ,  G06F1/3287

Abstract: Methods, systems, and devices for shallow hibernate power state are described. A memory system may include a memory array and a controller. The memory system may transition from a first power state having a first current to a second power state having a second current less than the first current, where the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components of the memory array. The memory system may initiate a timer after transitioning from the first power state to the second power state. The memory system may determine the timer satisfies a threshold and transition from the second power state to a third power state having a third current less than the second current based on the timer satisfying the threshold.

公开(公告)号：US12079479B2

公开(公告)日：2024-09-03

申请号：US17672026

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Chang H. Siau ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane.

公开(公告)号：US12019884B2

公开(公告)日：2024-06-25

申请号：US17651215

申请日：2022-02-15

Applicant: Micron Technology, Inc.

Inventor： Luca Porzio ,  Roberto Izzi ,  Christian M. Gyllenskog ,  Giuseppe Cariello ,  Jonathan S. Parry ,  Reshmi Basu

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0632 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0238 ,  G06F2212/7201

Abstract: Methods, systems, and devices for identification and storage of boot information at a memory system are described to support transferring boot information to higher reliability memory storage. A memory system may identify boot information stored at a memory array based on a command received from a host system, which may identify the boot information for the memory system, or based on performing a boot procedure with the host system, in which the boot information may be requested from the memory system. After identifying the boot information stored at the memory array, the memory system may move or transfer the boot information from physical addresses associated with lower reliable memory storage to physical addresses associated with higher reliable memory storage.

公开(公告)号：US20240161838A1

公开(公告)日：2024-05-16

申请号：US18505855

申请日：2023-11-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Nicola Ciocchini ,  Animesh Roy Chowdhury ,  Kishore Kumar Muchherla ,  Akira Goda ,  Jung Sheng Hoei ,  Niccolo’ Righetti ,  Jonathan S. Parry ,  Ugo Russo

IPC: G11C16/34 ,  G11C7/04 ,  G11C16/32

CPC classification number: G11C16/3431 ,  G11C7/04 ,  G11C16/32

Abstract: A system may include a memory device comprising a plurality of memory blocks, and a processing device to, responsive to receiving a request to read a memory block from the memory device, determine a time difference between a current time and a timestamp associated with the memory block, determine whether the time difference satisfies a first threshold increment criterion, responsive to determining that the time difference satisfies the first threshold increment criterion, increment a read counter associated with the memory block by a first increment value associated with the first threshold increment criterion, determine that the read counter associated with the memory block satisfies a threshold scan criterion, and responsive to determining that the read counter satisfies the threshold scan criterion, perform a media scan with respect to the memory block.