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公开(公告)号：US12131028B2
公开(公告)日：2024-10-29
申请号：US18121494
申请日：2023-03-14
发明人： Jeffrey S. McNeil , Jonathan S. Parry , Ugo Russo , Akira Goda , Kishore Kumar Muchherla , Violante Moschiano , Niccolo' Righetti , Silvia Beltrami
CPC分类号： G06F3/0611 , G06F3/0659 , G06F3/0679
摘要： Control logic in a memory device causes a first pulse to be applied to a plurality of word lines coupled to respective memory cells in a memory array during an erase operation. The control logic further causes a second pulse to be applied to a first set of word lines of the plurality of word lines to bias the first set of word lines to a first voltage. The control logic can cause a third pulse to be applied to a second set of word lines of the plurality of word lines to bias the second set of word lines to a second voltage and cause a fourth pulse to be applied to a source line of the memory array to erase the respective memory cells coupled to the first set of word lines and to program the respective memory cells coupled to the second set of word lines.
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公开(公告)号：US20240345750A1
公开(公告)日：2024-10-17
申请号：US18638471
申请日：2024-04-17
发明人： Deping He , Jonathan S. Parry
IPC分类号： G06F3/06 , G06F1/3234 , G06F1/3296
CPC分类号： G06F3/0634 , G06F1/3275 , G06F1/3296 , G06F3/0625 , G06F3/0659 , G06F3/0673
摘要： Methods, systems, and devices for host recovery for a stuck condition of a memory system are described. The host system may transmit a first command for the memory system to transition from a first power mode to a second power mode (e.g., low-power mode). In some cases, the host system may transmit a second command for the memory system to exit the second power mode shortly after transmitting the first command. The host system may activate a timer associated with a time-out condition for exiting the second power mode and may determine that a duration indicated by the timer expires. In some examples, the host system may transmit a third command for the memory system to perform a hardware reset operation based on determining that the duration of the timer expires.
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公开(公告)号：US20240330519A1
公开(公告)日：2024-10-03
申请号：US18624775
申请日：2024-04-02
CPC分类号： G06F21/79 , G06F12/0246 , G06F12/0253 , G06F21/54 , G06F21/602 , G06F21/107
摘要： Methods, systems, and devices for purging data from a memory device are described. A memory system may receive, from a host system, a command to write data to an address storing an encryption key in a first portion of the memory system that is configured to store secure information (e.g., a Replay Protected Memory Block). The encryption key may be configured to encrypt data associated with the host system that is stored in a second portion of the memory system. The memory system may then receive an indication of a purge command from the host system. The memory system may execute the purge command by transferring data from the first portion of the memory system to a third portion of the memory system configured to store secure information and erasing the data from the first portion of the memory system.
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公开(公告)号：US20240329721A1
公开(公告)日：2024-10-03
申请号：US18597462
申请日：2024-03-06
发明人： Deping He , Nadav Grosz , Jonathan S. Parry
IPC分类号： G06F1/3234 , G06F1/3287
CPC分类号： G06F1/3275 , G06F1/3287
摘要： Methods, systems, and devices for shallow hibernate power state are described. A memory system may include a memory array and a controller. The memory system may transition from a first power state having a first current to a second power state having a second current less than the first current, where the first power state is associated with executing received commands and the second power state is associated with deactivating one or more components of the memory array. The memory system may initiate a timer after transitioning from the first power state to the second power state. The memory system may determine the timer satisfies a threshold and transition from the second power state to a third power state having a third current less than the second current based on the timer satisfying the threshold.
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公开(公告)号：US12079479B2
公开(公告)日：2024-09-03
申请号：US17672026
申请日：2022-02-15
发明人： Chang H. Siau , Jonathan S. Parry
IPC分类号： G06F3/06
CPC分类号： G06F3/0611 , G06F3/0604 , G06F3/0659 , G06F3/0679
摘要： A memory device including a first plane group comprising a first plane, a second plane group comprising a second plane, a first input/output (I/O) interface configured to access the first plane group, and a second I/O interface configured to access the second plane group. The memory device further includes a controller operatively coupled to the first I/O interface via a first channel and operatively coupled to the second I/O interface via a second channel. The controller can transmit, via the first channel to the first I/O interface, a first command to execute a first memory access operation associated with the first plane. The controller can transmit, via the second channel to the second I/O interface, a second command to execute a second memory access operation associated with the second plane.
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公开(公告)号：US12019884B2
公开(公告)日：2024-06-25
申请号：US17651215
申请日：2022-02-15
发明人： Luca Porzio , Roberto Izzi , Christian M. Gyllenskog , Giuseppe Cariello , Jonathan S. Parry , Reshmi Basu
CPC分类号： G06F3/0632 , G06F3/0604 , G06F3/0659 , G06F3/0679 , G06F12/0238 , G06F2212/7201
摘要： Methods, systems, and devices for identification and storage of boot information at a memory system are described to support transferring boot information to higher reliability memory storage. A memory system may identify boot information stored at a memory array based on a command received from a host system, which may identify the boot information for the memory system, or based on performing a boot procedure with the host system, in which the boot information may be requested from the memory system. After identifying the boot information stored at the memory array, the memory system may move or transfer the boot information from physical addresses associated with lower reliable memory storage to physical addresses associated with higher reliable memory storage.
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7.发明公开公开(公告)号：US20240161838A1
公开(公告)日：2024-05-16
申请号：US18505855
申请日：2023-11-09
发明人： Nicola Ciocchini , Animesh Roy Chowdhury , Kishore Kumar Muchherla , Akira Goda , Jung Sheng Hoei , Niccolo’ Righetti , Jonathan S. Parry , Ugo Russo
CPC分类号： G11C16/3431 , G11C7/04 , G11C16/32
摘要： A system may include a memory device comprising a plurality of memory blocks, and a processing device to, responsive to receiving a request to read a memory block from the memory device, determine a time difference between a current time and a timestamp associated with the memory block, determine whether the time difference satisfies a first threshold increment criterion, responsive to determining that the time difference satisfies the first threshold increment criterion, increment a read counter associated with the memory block by a first increment value associated with the first threshold increment criterion, determine that the read counter associated with the memory block satisfies a threshold scan criterion, and responsive to determining that the read counter satisfies the threshold scan criterion, perform a media scan with respect to the memory block.
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公开(公告)号：US20240118971A1
公开(公告)日：2024-04-11
申请号：US18483091
申请日：2023-10-09
发明人： Kishore Kumar Muchherla , David Scott Ebsen , Akira Goda , Jonathan S. Parry , Vivek Shivhare , Suresh Rajgopal
CPC分类号： G06F11/1076 , G06F3/0619 , G06F3/0656 , G06F3/0659 , G06F3/0683
摘要： Methods, systems, and apparatuses include allocating a temporary parity buffer to a parity group. A write command is received that includes user data and is directed to a portion of memory included in a zone which is included in the parity group. A memory identifier is determined for the portion of memory. Parity group data is received from the temporary parity buffer using the memory identifier. Updated parity group data is determined using the parity group data and the user data. The updated parity group data is sent to the temporary parity buffer.
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公开(公告)号：US11922029B2
公开(公告)日：2024-03-05
申请号：US17863000
申请日：2022-07-12
发明人： Kishore Kumar Muchherla , Jonathan S. Parry , Nicola Ciocchini , Animesh Roy Chowdhury , Akira Goda , Jung Sheng Hoei , Niccolo' Righetti , Ugo Russo
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0653 , G06F3/0679
摘要： A system includes a memory device including multiple memory cells and a processing device operatively coupled to the memory device. The processing device is to receive a first read command at a first time. The first read command is with respect to a set of memory cells of the memory device. The processing device is further to receive a second read command at a second time. The second read command is with respect to the set of memory cells of the memory device. The processing device is further to increment a read counter for the memory device by a value reflecting a difference between the first time and the second time. The processing device is further to determine that a value of the read counter satisfies a threshold criterion. The processing device is further to perform a data integrity scan with respect to the set of memory cells.
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公开(公告)号：US20240053925A1
公开(公告)日：2024-02-15
申请号：US17888325
申请日：2022-08-15
发明人： Reshmi Basu , Jonathan S. Parry , Nitul Gohain
CPC分类号： G06F3/0659 , G06F3/0634 , G06F3/0679 , G06F3/0604 , G06F12/0253
摘要： Methods, systems, and devices for caching for a multiple-level memory device are described. First data may be received for writing to a memory device that include multiple-level cells that are programmable using multiple programming modes. Based on receiving the first data, the first data may be written to first multiple-level cells using a first programming mode. Based on writing the first data to the first multiple-level cells, the first data may be transferred from the first multiple-level cells to second multiple-level cells using a third programming mode. Later, second data writing to the memory device may be received. Based on receiving the second data, a determination of whether to write the second data to third multiple-level cells using the first programming mode or a second programming mode may be made based on available multiple-level cells that are ready for programming.
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