公开(公告)号：US20190108042A1

公开(公告)日：2019-04-11

申请号：US16117529

申请日：2018-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： GREGORY EDVENSON ,  JEREMY CHRITZ ,  DAVID HULTON

IPC: G06F9/448 ,  G06F9/30 ,  G06F15/18

Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include a first configurable logic unit configured to receive a first operand and a second operand; a second configurable logic unit configured to receive a third operand and the first calculated operand; a first switch configured to receive the first operand and a fourth operand and to output a first selected operand; and a second switch configured to receive the second calculated operand and the first selected operand.

公开(公告)号：US20230126741A1

公开(公告)日：2023-04-27

申请号：US18146120

申请日：2022-12-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JEREMY CHRITZ ,  DAVID HULTON

IPC: G06F3/06 ,  H04L9/06 ,  G06F12/0877

Abstract: Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

公开(公告)号：US20210026779A1

公开(公告)日：2021-01-28

申请号：US17068370

申请日：2020-10-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JEREMY CHRITZ ,  DAVID HULTON

IPC: G06F12/10 ,  G06F3/06

Abstract: Apparatuses and methods for managing a coherent memory are described. These may include one or more algorithmic logic units (ALUs) and an input/output (I/O) interface. The I/O interface may receive one or more commands and retrieve data from or write data to a memory device. Each command may contain a memory address portion associated with a memory device. The apparatus may also include a memory mapping unit and a device controller. The memory mapping unit may map the memory address to a memory portion of the memory device, and the device controller may communicate with the memory device to retrieve data from or write data to the memory device. The apparatus may be implemented as a processing element in a configurable logic block network, which may additionally include a control logic unit that receives programming instructions from an application and generate the one or more commands based on the instructions.

公开(公告)号：US20240201871A1

公开(公告)日：2024-06-20

申请号：US18428157

申请日：2024-01-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JEREMY CHRITZ ,  DAVID HULTON

IPC: G06F3/06 ,  G06F12/0877 ,  H04L9/06

CPC classification number: G06F3/0622 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0877 ,  H04L9/0631 ,  G06F2212/60

Abstract: Examples of systems and methods described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

公开(公告)号：US20220222384A1

公开(公告)日：2022-07-14

申请号：US17146274

申请日：2021-01-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： DAVID HULTON ,  JEREMY CHRITZ

IPC: G06F21/79 ,  G06F21/60 ,  G06F12/02 ,  G06F13/16 ,  G06F13/42 ,  G06F13/40

Abstract: Examples of systems and methods described herein provide for erasing an encrypted key used for data access to a non-volatile memory device. A memory controller may generate an encrypted key for data access to non-volatile memory devices; and, to provide security of data stored on the non-volatile memory devices, the memory controller may store the encrypted key in a local cache of the memory controller. The encrypted key may be erased responsive to losing power or powering down of memory controller. Advantageously, the data stored at the non-volatile memory device may not be accessed when the memory controller (or a computing device implementing the memory controller) loses power. Accordingly, if a malicious actor were to physically remove (or steal) a computing device implementing the memory controller (e.g., a laptop computer), in an attempt to acquire the data, the data stored on the non-volatile memory devices could not be accessed.

公开(公告)号：US20220075556A1

公开(公告)日：2022-03-10

申请号：US17016023

申请日：2020-09-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： DAVID HULTON ,  JEREMY CHRITZ

IPC: G06F3/06 ,  G06N3/08 ,  G06K9/62 ,  G06F13/16 ,  H04L9/06

Abstract: Examples of systems and method described herein provide for the processing of image codes (e.g., a binary embedding) at a memory system including a Hamming processing unit. Such images codes may generated by various endpoint computing devices, such as Internet of Things (IoT) computing devices, Such devices can generate a Hamming processing request, having an image code of the image, to compare that representation of the image to other images (e.g., in an image dataset) to identify a match or a set of neural network results. Advantageously, examples described herein may be used in neural networks to facilitate the processing of datasets, so as to increase the rate and amount of processing of such datasets. For example, comparisons of image codes can be performed “closer” to the memory devices, e.g., at a processing unit having memory devices.

公开(公告)号：US20240176916A1

公开(公告)日：2024-05-30

申请号：US18433095

申请日：2024-02-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JEREMY CHRITZ ,  DAVID HULTON

IPC: G06F21/79 ,  G06F12/14 ,  G06F13/16 ,  G06F21/31 ,  G06F21/60 ,  H04L9/06

CPC classification number: G06F21/79 ,  G06F12/1433 ,  G06F13/1668 ,  G06F21/31 ,  G06F21/602 ,  G06F21/604 ,  H04L9/0643

Abstract: Examples of systems and method described herein or generating, in a memory controller and/or memory device, access codes for memory regions of the memory device using authentication logic, and for accessing the memory device using the access codes. For example, a memory controller and/or a coupled memory device may generate access codes that a host computing device may include in a memory access request to access one or more memory regions of the memory device. Data read or written at the memory device may in some examples only be accessed in accordance with the access codes for memory regions of the memory device. Accordingly, the systems and methods described herein may provide security for specific memory regions of a memory device because the access code are updated periodically (e.g., based on obtained reset indication) or in accordance with an updated count value from a counter.

公开(公告)号：US20220276967A1

公开(公告)日：2022-09-01

申请号：US17664348

申请日：2022-05-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JEREMY CHRITZ ,  DAVID HULTON

IPC: G06F12/10 ,  G06F3/06

Abstract: Apparatuses and methods for managing a coherent memory are described. These may include one or more algorithmic logic units (ALUs) and an input/output (IO) interface. The I/O interface may receive one or more commands and retrieve data from or write data to a memory device. Each command may contain a memory address portion associated with a memory device. The apparatus may also include a memory mapping unit and a device controller. The memory mapping unit may map the memory address to a memory portion of the memory device, and the device controller may communicate with the memory device to retrieve data from or write data to the memory device. The apparatus may be implemented as a processing element in a configurable logic block network, which may additionally include a control logic unit that receives programming instructions from an application and generate the one or more commands based on the instructions.

公开(公告)号：US20220068430A1

公开(公告)日：2022-03-03

申请号：US17454443

申请日：2021-11-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： DAVID HULTON ,  TAMARA SCHMITZ ,  JONATHAN D. HARMS ,  JEREMY CHRITZ ,  KEVIN MAJERUS

IPC: G11C29/00 ,  G06F12/126 ,  G06F12/02 ,  G06F3/06

Abstract: Methods, apparatuses, and systems for repairing defective memory cells in regions of a memory array associated with high or low priority levels are disclosed. A repair address generator may be configured to generate a memory address map for repair (e.g., blowing fuses at a fuse circuit), depending on whether certain applications may operate at a high priority level indicative of a low bit error rate or a low priority level indicative of a higher bit error rate. For example, a specified error rate associated with a low priority level may correspond to a threshold error rate for certain applications, such as a neural network application that stores trained weights. Such neural network applications may access trained weights being partially stored in defective memory cells, with the least significant bits of such trained weights being stored in defective memory cells that are not repaired according to the memory address map.

公开(公告)号：US20220060410A1

公开(公告)日：2022-02-24

申请号：US17517544

申请日：2021-11-02

Applicant: MICRON TECHNOLOGY, INC.

Inventor： JEREMY CHRITZ ,  DAVID HULTON ,  JOHN SCHROETER ,  JOHN WATSON

IPC: H04L12/721

Abstract: A device comprising a plurality of antennas operable to transmit and receive communication packets via a plurality of communication protocols and an integrated circuit chip coupled to the plurality of antennas. The integrated circuit chip comprises a first and a second plurality of processing elements. The first plurality of processing elements operable to receive communication packets via a first one of a plurality of communication protocols and process an optimal route. The second plurality of processing elements communicatively coupled to the first plurality of processing elements and operable to determine the optimal route to transmit the communication packets from a source device to a destination device based, at least in part, on transmission characteristics associated with at least one of the source or destination devices.