公开(公告)号：US20250053506A1

公开(公告)日：2025-02-13

申请号：US18778627

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Emanuele CONFALONIERI ,  Marco SFORZIN

IPC: G06F12/02

Abstract: Provided is a device that includes an interface operatively coupled to a locked redundant array of independent disks including M (M>1) memory dice, the M memory dice stores stripes of data, and each stripe spanning over the M memory dice; and control circuitry that performs data compression on data to generate compressed data; stores the compressed data in the stripes; generates parity data of each stripe; determines, for each stripe, memory dice required to store the compressed data; determines, for each stripe, whether the memory dice required to store the compressed data in each stripe is N memory dice or less; where N is an integer less than M; and determines, for each stripe, which stripes will store the parity data of a respective stripe based on the determination of whether the memory dice required to store the compressed data in the respective stripe is N memory dice or less.

公开(公告)号：US20250094278A1

公开(公告)日：2025-03-20

申请号：US18778665

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  Emanuele CONFALONIERI ,  Daniele BALLUCHI ,  Danilo CARACCIO ,  Nicola DEL GATTO ,  Rishabh DUBEY

IPC: G06F11/10

Abstract: Provided in a central controller system, is a system and method to identify and mitigate errors on a die containing mission critical logical-to-physical addressing information. The logical-to-physical (L2P) addressing information is essential for translating logical memory addresses for uncompressed data to physical addresses for compressed data. When a die containing L2P data is detected as being corrupted, the corrupted data is corrected, and all the data is moved to an uncorrupted die at a specified offset from the original address of the die.

公开(公告)号：US20250086059A1

公开(公告)日：2025-03-13

申请号：US18778641

申请日：2024-07-19

Applicant: Micron Technology, Inc.

Inventor： Emanuele CONFALONIERI ,  Marco SFORZIN

IPC: G06F11/10 ,  G06F11/07 ,  H03M7/30

Abstract: Provided is a device that includes an interface operatively coupled to a locked redundant array of independent disks (LRAID) including M (M>1) memory dice, the M memory dice stores stripes of data, and each stripe spanning over the M memory dice; and control circuitry that performs data compression on data to generate compressed data; stores the compressed data in the stripes; generates parity data of each stripe; determines, for each stripe, memory dice required to store the compressed data; determines, for each stripe, whether memory dice required to store the compressed data in each stripe is N memory dice or less; where N is an integer less than M; and determines, for each stripe, which stripes will store the parity data of a respective stripe based on the determination of whether the memory dice required to store the compressed data in the respective stripe is N memory dice or less.

公开(公告)号：US20150032927A1

公开(公告)日：2015-01-29

申请号：US14455718

申请日：2014-08-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giulio ALBINI ,  Emanuele CONFALONIERI

IPC: G06F13/42 ,  G06F12/14

CPC classification number: G06F12/1466 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0673 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/14 ,  G06F13/1668 ,  G06F13/4036 ,  G06F13/4221 ,  G06F2212/1052

Abstract: Subject matter disclosed herein relates to an apparatus comprising memory and a controller, such as a controller which determines block locking states in association with operative transitions between two or more interfaces that share at least one block of memory. The apparatus may support single channel or multi-channel memory access, write protection state logic, or various interface priority schemes.

Abstract translation: 本文公开的主题涉及包括存储器和控制器的控制器，诸如控制器，其与共享至少一个存储器块的两个或多个接口之间的操作转换相关联地确定块锁定状态。 该装置可以支持单通道或多通道存储器访问，写保护状态逻辑或各种接口优先级方案。