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公开(公告)号：US08913448B2
公开(公告)日：2014-12-16
申请号：US13660768
申请日：2012-10-25
Applicant: Micron Technology, Inc.
Inventor： Robert Tamlyn , Debra M. Bell , Michael Roth , Eric A. Becker , Tyrel Z. Jensen
IPC: G11C7/00
CPC classification number: G11C29/028 , G11C7/1066 , G11C7/109 , G11C7/1093 , G11C7/222 , G11C29/022 , G11C29/023 , G11C2207/105
Abstract: Apparatuses and methods for capturing data in a memory are disclosed herein. An apparatus may include a command path and a data capture logic. The command path may be configured to receive a command signal and to delay the command signal with a delay based, at least in part, on a plurality of propagation delays. The data capture logic may be coupled to the command path and configured to receive the delayed command signal and a data strobe signal. The data capture logic may further be configured to capture data according to the data strobe signal responsive, at least in part, to receipt of the delayed command signal.
Abstract translation: 本文公开了用于在存储器中捕获数据的装置和方法。 装置可以包括命令路径和数据捕获逻辑。 命令路径可以被配置为接收命令信号并且至少部分地基于多个传播延迟延迟基于延迟的命令信号。 数据捕获逻辑可以耦合到命令路径并且被配置为接收延迟的命令信号和数据选通信号。 数据采集逻辑还可以被配置为至少部分地响应于接收延迟的命令信号而根据数据选通信号捕获数据。
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Patent Agency Ranking
公开(公告)号：US20230268927A1
公开(公告)日：2023-08-24
申请号：US17677724
申请日：2022-02-22
Applicant: Micron Technology, Inc.
Inventor： Eric A. Becker , Tyler J. Gomm
CPC classification number: H03M1/0617 , H03K3/0315 , H03M7/165 , G04F10/005
Abstract: A time to digital circuit may provide a time measurement of an event, or a time measurement of a duration between multiple events. Various electronic devices may include one or more time to digital circuits. A time to digital circuit may include circuitry to use Thermometer Code for measuring the duration of the time. For example, the time to digital circuit may generate alternating signals using a ring oscillator when receiving an indication of an event. Moreover, the time to digital circuit may convert the alternating signals to a consistent signal with only one transition between high and low signals in multiple consecutive signals. Furthermore, the time to digital circuit may correct erroneous signal values of the consistent signals when multiple transitions between high and low signals in multiple consecutive signals occurs.
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公开(公告)号：US11742868B1
公开(公告)日：2023-08-29
申请号：US17677724
申请日：2022-02-22
Applicant: Micron Technology, Inc.
Inventor： Eric A. Becker , Tyler J. Gomm
CPC classification number: H03M1/0617 , G04F10/005 , H03K3/0315 , H03M7/165
Abstract: A time to digital circuit may provide a time measurement of an event, or a time measurement of a duration between multiple events. Various electronic devices may include one or more time to digital circuits. A time to digital circuit may include circuitry to use Thermometer Code for measuring the duration of the time. For example, the time to digital circuit may generate alternating signals using a ring oscillator when receiving an indication of an event. Moreover, the time to digital circuit may convert the alternating signals to a consistent signal with only one transition between high and low signals in multiple consecutive signals. Furthermore, the time to digital circuit may correct erroneous signal values of the consistent signals when multiple transitions between high and low signals in multiple consecutive signals occurs.
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公开(公告)号：US20230197138A1
公开(公告)日：2023-06-22
申请号：US17558512
申请日：2021-12-21
Applicant: Micron Technology, Inc.
Inventor： Eric A. Becker , Tyler J. Gomm
IPC: G11C11/4074 , G11C11/4076 , G06F7/58
CPC classification number: G11C11/4074 , G11C11/4076 , G06F7/584 , G06F2207/581
Abstract: An apparatus having a power bus supplying power to a component of a memory device. The apparatus includes a noise source circuit generating a plurality of noise source signals that simulate a real-world noise. The apparatus can include a pulse generator circuit that receives the noise source signal and outputs at least one noise profile signal based on the noise source signal. A bus shorting circuit can be connected to the pulse generator circuit to receive the at least one noise profile signal. The bus shorting circuit can have at least one transistor connected between a first rail and a second rail of the power bus. Based on the at least one noise profile signal, the bus shorting circuit intermittently connects the at least one transistor between the first rail to the second rail to induce noise on the power bus.
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公开(公告)号：US11915739B2
公开(公告)日：2024-02-27
申请号：US17558512
申请日：2021-12-21
Applicant: Micron Technology, Inc.
Inventor： Eric A. Becker , Tyler J. Gomm
IPC: G11C5/14 , G06F7/58 , G11C11/401 , G11C11/4074 , G11C11/4076
CPC classification number: G11C11/4074 , G06F7/584 , G11C5/14 , G11C5/143 , G11C11/401 , G11C11/4076 , G06F2207/581
Abstract: An apparatus having a power bus supplying power to a component of a memory device. The apparatus includes a noise source circuit generating a plurality of noise source signals that simulate a real-world noise. The apparatus can include a pulse generator circuit that receives the noise source signal and outputs at least one noise profile signal based on the noise source signal. A bus shorting circuit can be connected to the pulse generator circuit to receive the at least one noise profile signal. The bus shorting circuit can have at least one transistor connected between a first rail and a second rail of the power bus. Based on the at least one noise profile signal, the bus shorting circuit intermittently connects the at least one transistor between the first rail to the second rail to induce noise on the power bus.
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公开(公告)号：US20140119141A1
公开(公告)日：2014-05-01
申请号：US13660768
申请日：2012-10-25
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Robert Tamlyn , Debra M. Bell , Michael Roth , Eric A. Becker , Tyrel Z. Jensen
IPC: G11C8/18
CPC classification number: G11C29/028 , G11C7/1066 , G11C7/109 , G11C7/1093 , G11C7/222 , G11C29/022 , G11C29/023 , G11C2207/105
Abstract: Apparatuses and methods for capturing data in a memory are disclosed herein. An apparatus may include a command path and a data capture logic. The command path may be configured to receive a command signal and to delay the command signal with a delay based, at least in part, on a plurality of propagation delays. The data capture logic may be coupled to the command path and configured to receive the delayed command signal and a data strobe signal. The data capture logic may further be configured to capture data according to the data strobe signal responsive, at least in part, to receipt of the delayed command signal.
Abstract translation: 本文公开了用于在存储器中捕获数据的装置和方法。 装置可以包括命令路径和数据捕获逻辑。 命令路径可以被配置为接收命令信号并且至少部分地基于多个传播延迟延迟基于延迟的命令信号。 数据捕获逻辑可以耦合到命令路径并且被配置为接收延迟的命令信号和数据选通信号。 数据采集逻辑还可以被配置为至少部分地响应于接收延迟的命令信号而根据数据选通信号捕获数据。
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