公开(公告)号：US08913448B2

公开(公告)日：2014-12-16

申请号：US13660768

申请日：2012-10-25

Applicant: Micron Technology, Inc.

Inventor： Robert Tamlyn ,  Debra M. Bell ,  Michael Roth ,  Eric A. Becker ,  Tyrel Z. Jensen

IPC: G11C7/00

CPC classification number: G11C29/028 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C2207/105

Abstract: Apparatuses and methods for capturing data in a memory are disclosed herein. An apparatus may include a command path and a data capture logic. The command path may be configured to receive a command signal and to delay the command signal with a delay based, at least in part, on a plurality of propagation delays. The data capture logic may be coupled to the command path and configured to receive the delayed command signal and a data strobe signal. The data capture logic may further be configured to capture data according to the data strobe signal responsive, at least in part, to receipt of the delayed command signal.

Abstract translation: 本文公开了用于在存储器中捕获数据的装置和方法。 装置可以包括命令路径和数据捕获逻辑。 命令路径可以被配置为接收命令信号并且至少部分地基于多个传播延迟延迟基于延迟的命令信号。 数据捕获逻辑可以耦合到命令路径并且被配置为接收延迟的命令信号和数据选通信号。 数据采集​​逻辑还可以被配置为至少部分地响应于接收延迟的命令信号而根据数据选通信号捕获数据。

公开(公告)号：US20140119141A1

公开(公告)日：2014-05-01

申请号：US13660768

申请日：2012-10-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Robert Tamlyn ,  Debra M. Bell ,  Michael Roth ,  Eric A. Becker ,  Tyrel Z. Jensen

IPC: G11C8/18

CPC classification number: G11C29/028 ,  G11C7/1066 ,  G11C7/109 ,  G11C7/1093 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023 ,  G11C2207/105

Abstract: Apparatuses and methods for capturing data in a memory are disclosed herein. An apparatus may include a command path and a data capture logic. The command path may be configured to receive a command signal and to delay the command signal with a delay based, at least in part, on a plurality of propagation delays. The data capture logic may be coupled to the command path and configured to receive the delayed command signal and a data strobe signal. The data capture logic may further be configured to capture data according to the data strobe signal responsive, at least in part, to receipt of the delayed command signal.

Abstract translation: 本文公开了用于在存储器中捕获数据的装置和方法。 装置可以包括命令路径和数据捕获逻辑。 命令路径可以被配置为接收命令信号并且至少部分地基于多个传播延迟延迟基于延迟的命令信号。 数据捕获逻辑可以耦合到命令路径并且被配置为接收延迟的命令信号和数据选通信号。 数据采集​​逻辑还可以被配置为至少部分地响应于接收延迟的命令信号而根据数据选通信号捕获数据。

公开(公告)号：US20240241671A1

公开(公告)日：2024-07-18

申请号：US18513438

申请日：2023-11-17

Applicant: Micron Technology, Inc.

Inventor： Kevin G. Werhane ,  Vijayakrishna J. Vankayala ,  Tyrel Z. Jensen

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, apparatuses, and systems related to calibrating memory circuitry according to externally provided reference voltage are described. A memory device may include a calibration control logic that at least isolates an internal reference voltage from an internal buffer. The internal buffer may receive and process the externally provided reference voltage instead of command-address signals for calibration purposes.

公开(公告)号：US11081166B1

公开(公告)日：2021-08-03

申请号：US17000202

申请日：2020-08-21

Applicant: Micron Technology, Inc.

Inventor： Kevin G. Werhane ,  Jason M. Johnson ,  Yoshinori Fujiwara ,  Tyrel Z. Jensen ,  Daniel S. Miller ,  David E. Jefferson ,  Vivek Kotti

IPC: G11C11/408 ,  G11C11/22

Abstract: Methods, systems, and devices for memory device random option inversion are described. A memory device may use a second set of fuses to selectively invert options associated with a first set of fuses (e.g., blown fuses). The first set of fuses may output a first set of logic states. Option inversion logic circuitry may perform decoding based on a second set of logic states output by the second set of fuses to identify logic states of the second set of logic states that match the first set of logic states. Based on identifying the logic states, the option inversion logic circuitry may select either a logic state of the first set of logic states or an inverted logic state corresponding to the logic state, and store the selected logic state in a latch of the memory device.