公开(公告)号：US20220206712A1

公开(公告)日：2022-06-30

申请号：US17382615

申请日：2021-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto Siciliani ,  Floriano Montemurro

IPC: G06F3/06 ,  G06F9/48

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform a program operation and in response to the command to perform the program operation, begin execution of the program operation. The controller might be further configured to while executing the program operation, receive a command to perform a read operation; in response to the command to perform the read operation, suspend the execution of the program operation; and with the execution of the program operation suspended, execute the read operation.

公开(公告)号：US11907574B2

公开(公告)日：2024-02-20

申请号：US17382615

申请日：2021-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto Siciliani ,  Floriano Montemurro

IPC: G06F3/06 ,  G06F9/48

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F9/485

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform a program operation and in response to the command to perform the program operation, begin execution of the program operation. The controller might be further configured to while executing the program operation, receive a command to perform a read operation; in response to the command to perform the read operation, suspend the execution of the program operation; and with the execution of the program operation suspended, execute the read operation.

公开(公告)号：US20220208273A1

公开(公告)日：2022-06-30

申请号：US17382619

申请日：2021-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto Siciliani ,  Floriano Montemurro ,  Eric N. Lee ,  Dheeraj Srinivasan

IPC: G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  G11C7/10

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation; and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.

公开(公告)号：US12189993B2

公开(公告)日：2025-01-07

申请号：US18407876

申请日：2024-01-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto Siciliani ,  Floriano Montemurro

IPC: G06F3/06 ,  G06F9/48

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.

公开(公告)号：US20240143235A1

公开(公告)日：2024-05-02

申请号：US18407876

申请日：2024-01-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto Siciliani ,  Floriano Montemurro

IPC: G06F3/06 ,  G06F9/48

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0679 ,  G06F9/485

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.

公开(公告)号：US11735268B2

公开(公告)日：2023-08-22

申请号：US17382619

申请日：2021-07-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Umberto Siciliani ,  Floriano Montemurro ,  Eric N. Lee ,  Dheeraj Srinivasan

IPC: G11C16/14 ,  G11C16/10 ,  G11C7/10 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C7/106 ,  G11C7/1063 ,  G11C16/102 ,  G11C16/26

Abstract: Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation; and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.