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59 条记录 (耗时 0.019 秒)

    STATUS POLLING BASED ON DIE-GENERATED PULSED SIGNAL
    2.
    发明申请
    STATUS POLLING BASED ON DIE-GENERATED PULSED SIGNAL 有权

    公开(公告)号：US20230024167A1

    公开(公告)日：2023-01-26

    申请号：US17590650

    申请日：2022-02-01

    申请人： Micron Technology, Inc.

    发明人： Eric N. Lee ,  Dheeraj Srinivasan

    IPC分类号： G06F3/06

    摘要： A memory system includes multiple dice having multiple planes. A processing device is coupled to the dice and performs controller operations including receiving a status indicator signal comprising a pulse that is asserted by one or more planes of the multiple dice. In response to receiving the pulse, the processing device performs at least one of: a first status check of dice operations being performed by the multiple dice at an expiration of a polling delay period; or a second status check of the dice operations in response to detecting the pulse being deasserted. The processing device terminates performances of status checks while the status indicator signal remains deasserted.

    MEMORY DEVICES FOR SUSPEND AND RESUME OPERATIONS
    3.
    发明申请
    MEMORY DEVICES FOR SUSPEND AND RESUME OPERATIONS 有权

    公开(公告)号：US20220208273A1

    公开(公告)日：2022-06-30

    申请号：US17382619

    申请日：2021-07-22

    申请人： MICRON TECHNOLOGY, INC.

    发明人： Umberto Siciliani ,  Floriano Montemurro ,  Eric N. Lee ,  Dheeraj Srinivasan

    IPC分类号： G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  G11C7/10

    摘要： Memory devices might include an array of memory cells and a controller configured to access the array of memory cells. The controller might be further configured to receive a command to perform an erase operation; and in response to the command to perform the erase operation, begin execution of the erase operation. The controller might be further configured to while executing the erase operation, receive a command to perform a program operation; in response to the command to perform the program operation, suspend the execution of the erase operation; and with the execution of the erase operation suspended, execute the program operation.

    APPARATUSES AND METHODS FOR AUTOMATED DYNAMIC WORD LINE START VOLTAGE
    5.
    发明申请
    APPARATUSES AND METHODS FOR AUTOMATED DYNAMIC WORD LINE START VOLTAGE 有权

    公开(公告)号：US20210057031A1

    公开(公告)日：2021-02-25

    申请号：US17090067

    申请日：2020-11-05

    申请人： Micron Technology, Inc.

    发明人： Dheeraj Srinivasan ,  Jeffrey M. Tsai ,  Ali Mohammadzadeh ,  Terry M. Grunzke

    IPC分类号： G11C16/08 ,  G11C16/12 ,  G06F3/06 ,  G11C8/08

    摘要： The present disclosure relates to apparatuses and methods for an automated dynamic word line start voltage. An example apparatus includes a controller and a memory device. The memory device is configured to maintain, internal to the memory device, a status of a number of open blocks in the memory device. The status can include a programming operation being initiated in the respective number of open blocks. Responsive to receipt of, from the controller, a request to direct initiation of the programming operation to a word line, determine a group of memory cells associated with the word line that programs first relative to other groups of memory cells associated with the word line and maintain, included in the status of an open block, a voltage at which the group of memory cells is the first group to program.

    BITLINE DRIVER ISOLATION FROM PAGE BUFFER CIRCUITRY IN MEMORY DEVICE
    9.
    发明申请
    BITLINE DRIVER ISOLATION FROM PAGE BUFFER CIRCUITRY IN MEMORY DEVICE 有权

    公开(公告)号：US20220180936A1

    公开(公告)日：2022-06-09

    申请号：US17678960

    申请日：2022-02-23

    申请人： Micron Technology, Inc.

    发明人： Violante Moschiano ,  Dheeraj Srinivasan ,  Andrea D'Alessandro

    IPC分类号： G11C16/24 ,  G11C16/04 ,  G11C16/26

    摘要： A page buffer circuit in a memory device includes a logic element configured to perform a series of calculations pertaining to one or more memory access operations and generate a plurality of calculation results associated with the series of calculations and a dynamic memory element coupled with the logic element and configured to store the plurality of calculation results. The page buffer circuit further includes an isolation element coupled between the logic element and the dynamic memory element, the isolation element to permit a calculation result from the logic element to pass to the dynamic memory element when activated and a circuit coupled to the dynamic memory element and configured to perform pre-charging operations associated with the one or more memory access operations and based at least in part on the plurality of calculation results stored in the dynamic memory element. The circuit coupled to the dynamic memory element can perform a first operation on the memory array based at least in part on a first calculation result stored in the dynamic memory element during a first period of time when the isolation element is deactivated to disconnect the logic element from the dynamic memory element, and the logic element is configured to concurrently generate a second calculation result during the first period of time.

    RESUMPTION OF PROGRAM OR ERASE OPERATIONS IN MEMORY
    10.
    发明申请
    RESUMPTION OF PROGRAM OR ERASE OPERATIONS IN MEMORY 有权

    公开(公告)号：US20220165340A1

    公开(公告)日：2022-05-26

    申请号：US17102876

    申请日：2020-11-24

    申请人： Micron Technology, Inc.

    发明人： Eric N. Lee ,  Dheeraj Srinivasan

    IPC分类号： G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C7/10

    摘要： A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.