公开(公告)号：US11609712B2

公开(公告)日：2023-03-21

申请号：US17320658

申请日：2021-05-14

Applicant: Micron Technology, Inc.

Inventor： Christina Papagianni ,  Foroozan Koushan

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/34

Abstract: A first write operation is performed to write a first portion of a set of host data to a first location of a memory device. It is determined whether a first elapsed time since the first operation is performed does not satisfy a time condition. Responsive to determining that the first elapsed time does not satisfy the time condition, a second write operation is performed to write a second portion of the set of host data to a second location of the memory device not adjacent to the first location.

公开(公告)号：US11037638B1

公开(公告)日：2021-06-15

申请号：US16715565

申请日：2019-12-16

Applicant: Micron Technology, Inc.

Inventor： Christina Papagianni ,  Foroozan Koushan

IPC: G06F12/00 ,  G11C16/34

Abstract: A request to write a set of host data is received. A first plurality of write operations is performed to write a first portion of the set of host data to a first set of memory cells of the memory device arranged in a first pattern. The first set of memory cells arranged in the first pattern comprises alternating memory cells on each word line of the memory device and excludes a second set of memory cells adjacent to the first set of memory cells. A second plurality of write operations is performed to write a second portion of the set of host data to the second set of memory cells arranged in a second pattern. The second set of memory cells arranged in the second pattern comprises other alternating memory cells on each word line of the memory device adjacent to the first set of memory cells.

公开(公告)号：US11694727B2

公开(公告)日：2023-07-04

申请号：US17866903

申请日：2022-07-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Foroozan Koushan ,  Jayasree Nayar ,  Ji-Hye Gale Shin

IPC: G11C5/02 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35

CPC classification number: G11C5/025 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  G11C2213/75

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

公开(公告)号：US20220351755A1

公开(公告)日：2022-11-03

申请号：US17866903

申请日：2022-07-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Foroozan Koushan ,  Jayasree Nayar ,  Ji-Hye Gale Shin

IPC: G11C5/02 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

公开(公告)号：US11417368B2

公开(公告)日：2022-08-16

申请号：US17181125

申请日：2021-02-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Foroozan Koushan ,  Jayasree Nayar ,  Ji-Hye Gale Shin

IPC: G11C16/04 ,  G11C5/02 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

公开(公告)号：US20220189512A1

公开(公告)日：2022-06-16

申请号：US17181125

申请日：2021-02-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Foroozan Koushan ,  Jayasree Nayar ,  Ji-Hye Gale Shin

IPC: G11C5/02 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

公开(公告)号：US20210272636A1

公开(公告)日：2021-09-02

申请号：US17320658

申请日：2021-05-14

Applicant: Micron Technology, Inc.

Inventor： Christina Papagianni ,  Foroozan Koushan

IPC: G11C16/34

Abstract: A first write operation is performed to write a first portion of a set of host data to a first location of a memory device. It is determined whether a first elapsed time since the first operation is performed does not satisfy a time condition. Responsive to determining that the first elapsed time does not satisfy the time condition, a second write operation is performed to write a second portion of the set of host data to a second location of the memory device not adjacent to the first location.

公开(公告)号：US20210181976A1

公开(公告)日：2021-06-17

申请号：US16715565

申请日：2019-12-16

Applicant: Micron Technology, Inc.

Inventor： Christina Papagianni ,  Foroozan Koushan

IPC: G06F3/06

Abstract: A request to write a set of host data is received. A first plurality of write operations is performed to write a first portion of the set of host data to a first set of memory cells of the memory device arranged in a first pattern. The first set of memory cells arranged in the first pattern comprises alternating memory cells on each word line of the memory device and excludes a second set of memory cells adjacent to the first set of memory cells. A second plurality of write operations is performed to write a second portion of the set of host data to the second set of memory cells arranged in a second pattern. The second set of memory cells arranged in the second pattern comprises other alternating memory cells on each word line of the memory device adjacent to the first set of memory cells.