公开(公告)号：US20210343346A1

公开(公告)日：2021-11-04

申请号：US17373701

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Ji-Hye Shin ,  Foroozan S. Koushan ,  Tomoko Iwasaki ,  Jayasree Nayar

IPC: G11C16/12 ,  G11C16/34 ,  G06F3/06

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations that include determining a verify reference voltage associated with a logic state of a memory cell of the memory device, the verify reference voltage defining a target voltage level of a threshold voltage associated with the logic state; determining an amount of voltage compensation based on a thermal profile associated with a heat to be applied to the memory device, the thermal profile comprising a temperature associated with the heat and a period of time the heat is to be applied to the memory device; and updating the verify reference voltage using the amount of voltage compensation for an expected shift in the threshold voltage of the memory cell after the heat is applied to the memory device.

公开(公告)号：US11735267B2

公开(公告)日：2023-08-22

申请号：US17373701

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Ji-Hye Shin ,  Foroozan S. Koushan ,  Tomoko Iwasaki ,  Jayasree Nayar

IPC: G11C16/00 ,  G11C16/12 ,  G11C16/34 ,  G06F3/06 ,  G11C16/26

CPC classification number: G11C16/12 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/3459 ,  G11C16/26

Abstract: A system includes a memory device and a processing device, operatively coupled with the memory device. The processing device is configured to perform operations that include determining a verify reference voltage associated with a logic state of a memory cell of the memory device, the verify reference voltage defining a target voltage level of a threshold voltage associated with the logic state; determining an amount of voltage compensation based on a thermal profile associated with a heat to be applied to the memory device, the thermal profile comprising a temperature associated with the heat and a period of time the heat is to be applied to the memory device; and updating the verify reference voltage using the amount of voltage compensation for an expected shift in the threshold voltage of the memory cell after the heat is applied to the memory device.

公开(公告)号：US11069412B2

公开(公告)日：2021-07-20

申请号：US16714369

申请日：2019-12-13

Applicant: Micron Technology, Inc.

Inventor： Ji-Hye Shin ,  Foroozan S. Koushan ,  Tomoko Iwasaki ,  Jayasree Nayar

IPC: G11C16/12 ,  G11C16/34 ,  G06F3/06 ,  G11C16/26

Abstract: A logic state to be stored at a memory cell of a memory device is determined, where the logic state is to be represented by a threshold voltage stored at the memory cell. A verify reference voltage associated with the logic state is determined. The verify reference voltage defines a target voltage level of the threshold voltage associated with the logic state. The verify reference voltage is updated using an amount of compensation for an expected shift in the threshold voltage of the memory cell after heat is applied to the memory device. Before the heat is applied to the memory device, a plurality of sets of multiple programming pulses to the memory cell is applied until a threshold condition is satisfied. The threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell to the updated verify reference voltage.

公开(公告)号：US11694727B2

公开(公告)日：2023-07-04

申请号：US17866903

申请日：2022-07-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Foroozan Koushan ,  Jayasree Nayar ,  Ji-Hye Gale Shin

IPC: G11C5/02 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35

CPC classification number: G11C5/025 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  G11C2213/75

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

公开(公告)号：US20220351755A1

公开(公告)日：2022-11-03

申请号：US17866903

申请日：2022-07-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Foroozan Koushan ,  Jayasree Nayar ,  Ji-Hye Gale Shin

IPC: G11C5/02 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

公开(公告)号：US11417368B2

公开(公告)日：2022-08-16

申请号：US17181125

申请日：2021-02-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Foroozan Koushan ,  Jayasree Nayar ,  Ji-Hye Gale Shin

IPC: G11C16/04 ,  G11C5/02 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

公开(公告)号：US20220189512A1

公开(公告)日：2022-06-16

申请号：US17181125

申请日：2021-02-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Foroozan Koushan ,  Jayasree Nayar ,  Ji-Hye Gale Shin

IPC: G11C5/02 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

公开(公告)号：US20210183448A1

公开(公告)日：2021-06-17

申请号：US16714369

申请日：2019-12-13

Applicant: Micron Technology, Inc.

Inventor： Ji-Hye Shin ,  Foroozan S. Koushan ,  Tomoko Iwasaki ,  Jayasree Nayar

IPC: G11C16/12 ,  G11C16/34 ,  G06F3/06

Abstract: A logic state to be stored at a memory cell of a memory device is determined, where the logic state is to be represented by a threshold voltage stored at the memory cell. A verify reference voltage associated with the logic state is determined. The verify reference voltage defines a target voltage level of the threshold voltage associated with the logic state. The verify reference voltage is updated using an amount of compensation for an expected shift in the threshold voltage of the memory cell after heat is applied to the memory device. Before the heat is applied to the memory device, a plurality of sets of multiple programming pulses to the memory cell is applied until a threshold condition is satisfied. The threshold condition is associated with a relative magnitude of the threshold voltage of the memory cell to the updated verify reference voltage.