公开(公告)号：US20240330174A1

公开(公告)日：2024-10-03

申请号：US18608251

申请日：2024-03-18

Applicant: Micron Technology, Inc.

Inventor： Shawn Storm ,  Joseph A. Oberle ,  Ji-Hye Gale Shin

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: A method includes configuring a memory system with a first set of operating characteristics corresponding to a first thermal voltage model, monitoring operation of the memory system, selecting a second thermal voltage model based on the monitored operation of the memory system, configuring the memory system with a second set of operating characteristics corresponding to the second thermal voltage model, and writing data to the memory system configured with the second set of operating characteristics.

公开(公告)号：US20240071531A1

公开(公告)日：2024-02-29

申请号：US18239193

申请日：2023-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Hong-Yan Chen ,  Pamela Castalino ,  Priya Vemparala Guruswamy ,  Jun Xu ,  Gianluca Nicosia ,  Ji-Hye Gale Shin

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12

CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/102 ,  G11C16/12

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a target level based on a compensation value of a program command. The controller is further configured to sense a threshold voltage of the selected memory cell. The controller is further configured to in response to the compensation value having a first value and the threshold voltage being greater than a first program verify level, inhibit programming of the selected memory cell. The controller is further configured to in response to the compensation value having a second value different from the first value and the threshold voltage being greater than a second program verify level less than the first program verify level, inhibit programming of the selected memory cell.

公开(公告)号：US11694727B2

公开(公告)日：2023-07-04

申请号：US17866903

申请日：2022-07-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Foroozan Koushan ,  Jayasree Nayar ,  Ji-Hye Gale Shin

IPC: G11C5/02 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35

CPC classification number: G11C5/025 ,  H10B41/35 ,  H10B41/41 ,  H10B43/35 ,  G11C2213/75

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

公开(公告)号：US20220351755A1

公开(公告)日：2022-11-03

申请号：US17866903

申请日：2022-07-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Foroozan Koushan ,  Jayasree Nayar ,  Ji-Hye Gale Shin

IPC: G11C5/02 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

公开(公告)号：US11417368B2

公开(公告)日：2022-08-16

申请号：US17181125

申请日：2021-02-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Foroozan Koushan ,  Jayasree Nayar ,  Ji-Hye Gale Shin

IPC: G11C16/04 ,  G11C5/02 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.

公开(公告)号：US20220189512A1

公开(公告)日：2022-06-16

申请号：US17181125

申请日：2021-02-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Foroozan Koushan ,  Jayasree Nayar ,  Ji-Hye Gale Shin

IPC: G11C5/02 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and a heater. The array of memory cells might include a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines might be connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The heater might be adjacent to an end of each access line of the plurality of access lines.