公开(公告)号：US20240155847A1

公开(公告)日：2024-05-09

申请号：US18484629

申请日：2023-10-11

Applicant: Micron Technology, Inc.

Inventor： Giorgio SERVALLI ,  Ashonita A. CHAVAN

IPC: H10B53/30

CPC classification number: H10B53/30

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a conductive plate, a top electrode in contact with the conductive plate and shared by a plurality of bottom electrodes included in the integrated assembly, a bottom electrode having a top surface, a bottom surface, and an exterior circumferential surface, and a ferroelectric insulator that separates the top electrode from the bottom electrode. In some implementations, a support structure is not present between a top surface of the ferroelectric insulator and a bottom surface of the conductive plate. The integrated assembly may include a leaker device having a top surface, a bottom surface in contact with the top surface of the bottom electrode, and an exterior circumferential surface. The leaker device may be configured to discharge charge from the bottom electrode to the conductive plate.

公开(公告)号：US20230397434A1

公开(公告)日：2023-12-07

申请号：US17812233

申请日：2022-07-13

Applicant: Micron Technology, Inc.

Inventor： Marcello MARIANI ,  Giorgio SERVALLI

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: A memory device includes an array of memory cells. A memory cell includes a transistor with a pillar that includes an upper source/drain, a lower source/drain, and a channel between the upper source/drain and the lower source/drain. The transistor includes a gate that is part of a gate line and that is proximate to the channel. The memory cell includes a capacitor having a bottom electrode, an insulator, and a top electrode. The memory cell includes a conductive contact region that couples the transistor and the capacitor and that includes the upper source/drain, a first conductive region having a right surface that abuts the upper source/drain and having a left surface that contacts a first insulator line, and a second conductive region having a left surface that abuts the upper source/drain and having a right surface that contacts a second insulator line that is parallel to the first insulator line.

公开(公告)号：US20240428839A1

公开(公告)日：2024-12-26

申请号：US18826719

申请日：2024-09-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Angelo VISCONTI ,  Giorgio SERVALLI

IPC: G11C11/22

Abstract: At least one portion of a memory array may be arranged to provide high density non-volatile random access memory (HIGH DENSITY NON-VOLATILE RAM) while at least one other portion of the memory array may be arranged to provide dynamic random access memory (DRAM)-like memory. In some examples, the memory array may be arranged by programming one or more configuration devices. In some examples, the configuration device may include one or more switches to couple one or more memory cells to a sense amplifier. In some examples, the configuration device may include fuses and/or antifuses to couple one or more memory cells to a sense amplifier. In some examples, the portions of the memory array may be reconfigurable from one arrangement to another arrangement.

公开(公告)号：US20240324175A1

公开(公告)日：2024-09-26

申请号：US18731738

申请日：2024-06-03

Applicant: Micron Technology, Inc.

Inventor： Giorgio SERVALLI ,  Marcello MARIANI ,  Antonino RIGANO ,  Marcello CALABRESE

IPC: H10B12/00 ,  H01L25/065

CPC classification number: H10B12/30 ,  H01L25/0655 ,  H10B12/033 ,  H10B12/48

Abstract: Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an integrated assembly includes a pillar having an upper source/drain, a middle source/drain, a lower source/drain, an upper channel between the upper source/drain and the middle source/drain, and a lower channel between the middle source/drain and the lower source/drain. The integrated assembly includes a gate pair that includes a first gate and a second gate. The first gate is positioned on a first side of the pillar at a first height, and the second gate is positioned on a second side of the pillar, that is opposite the first side, at a second height that is different from the first height. The integrated assembly includes a capacitor that is electrically coupled with the upper source/drain. Some implementations include methods of forming the various structures, integrated assemblies, and memory devices.

公开(公告)号：US20230352073A1

公开(公告)日：2023-11-02

申请号：US17732885

申请日：2022-04-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Angelo VISCONTI ,  Giorgio SERVALLI

IPC: G11C11/22

CPC classification number: G11C11/2255 ,  G11C11/221 ,  G11C11/2273

Abstract: At least one portion of a memory array may be arranged to provide high density non-volatile random access memory (HIGH DENSITY NON-VOLATILE RAM) while at least one other portion of the memory array may be arranged to provide dynamic random access memory (DRAM)-like memory. In some examples, the memory array may be arranged by programming one or more configuration devices. In some examples, the configuration device may include one or more switches to couple one or more memory cells to a sense amplifier. In some examples, the configuration device may include fuses and/or antifuses to couple one or more memory cells to a sense amplifier. In some examples, the portions of the memory array may be reconfigurable from one arrangement to another arrangement.

公开(公告)号：US20230236753A1

公开(公告)日：2023-07-27

申请号：US17854639

申请日：2022-06-30

Applicant: Micron Technology, Inc.

Inventor： Marco SFORZIN ,  Angelo VISCONTI ,  Giorgio SERVALLI ,  Daniele BALLUCHI ,  Paolo AMATO

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0616 ,  G06F3/0673

Abstract: Provided is a computing system including a memory system in communication with a host, to store data therein. The memory system includes a memory having a plurality of memory components coupled to the controller via a memory interface; and a memory controller configured to communicate with the memory to control data transmission and performing scrubbing operation of the memory components and detecting a region of the memory to be sanitized and performing a sanitization operation of the detected region to prevent the occurrence of failure.