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    Memory devices configured to apply different weights to different strings of memory cells coupled to a data line and methods
    1.
    发明授权
    Memory devices configured to apply different weights to different strings of memory cells coupled to a data line and methods 有权
    配置为将不同的权重应用于耦合到数据线和方法的不同存储器单元串的存储器件

    公开(公告)号：US09105330B1

    公开(公告)日：2015-08-11

    申请号：US13864659

    申请日：2013-04-17

    Applicant: Micron Technology, Inc.

    Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca de Santis ,  Tommaso Vali

    IPC: G11C15/00

    CPC classification number: G11C16/28 ,  G11C15/00 ,  G11C15/046 ,  G11C16/0483

    Abstract: Memory devices and methods are disclosed. One such method compares input data to stored data in a memory device and includes applying a first weight factor to a first string of memory cells coupled to a data line, where a first bit of the stored data is stored in the first string of memory cells; applying a second weight factor to a second string of memory cells coupled to the data line, where a second bit of the stored data is stored in the second string of memory cells; comparing a first bit of input data to the first bit of the stored data while the first weight factor is applied to the first string of memory cells; and comparing a second bit of the input data to the second bit of the stored data while the second weight factor is applied to the second string of memory cells.

    Abstract translation: 公开了存储器件和方法。 一种这样的方法将输入数据与存储器件中的存储数据进行比较，并且包括将第一加权因子应用于耦合到数据线的存储器单元的第一串，其中存储的数据的第一位被存储在第一存储单元串中 ; 将第二加权因子应用于耦合到所述数据线的第二存储单元串，其中所述存储数据的第二位存储在所述第二存储单元串中; 将第一加权因子应用于第一串存储器单元时，将第一比特的输入数据与存储数据的第一比较; 以及将所述输入数据的第二位与存储的数据的第二位进行比较，同时将所述第二权重因子应用于所述第二存储单元串。

    Apparatuses and methods for concurrently accessing different memory planes of a memory
    2.
    发明授权
    Apparatuses and methods for concurrently accessing different memory planes of a memory 有权

    公开(公告)号：US11955204B2

    公开(公告)日：2024-04-09

    申请号：US17959078

    申请日：2022-10-03

    Applicant: Micron Technology, Inc.

    Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

    IPC: G06F3/06 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32

    CPC classification number: G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2209

    Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY
    3.
    发明申请
    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY 审中-公开

    公开(公告)号：US20180366167A1

    公开(公告)日：2018-12-20

    申请号：US16109628

    申请日：2018-08-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

    IPC: G11C7/22 ,  G11C16/26 ,  G11C16/32

    Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY
    4.
    发明申请
    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY 有权
    用于同时访问存储器的不同存储器的设备和方法

    公开(公告)号：US20160048343A1

    公开(公告)日：2016-02-18

    申请号：US14461152

    申请日：2014-08-15

    Applicant: Micron Technology, Inc.

    Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

    IPC: G06F3/06

    CPC classification number: G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2209

    Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

    Abstract translation: 本文公开了用于对不同存储器平面执行并发存储器访问操作的装置和方法。 示例性装置可以包括具有多个存储器平面的存储器阵列。 多个存储器平面中的每一个包括多个存储单元。 该装置还可以包括被配置为接收一组存储器命令和地址对的控制器。 该组存储器命令和地址对的每个存储器命令和地址对可以与多个存储器平面中的相应存储器平面相关联。 内部控制器可以被配置为与存储器命令和地址组组的存储器命令组和地址对组中的每个存储器命令和地址对相关联地执行存储器访问操作，而不管与组的对相关联的页面类型（ 例如，即使两个或多个存储器命令和地址对可以与不同的页面类型相关联）。

    Apparatuses and methods for concurrently accessing different memory planes of a memory
    5.
    发明授权
    Apparatuses and methods for concurrently accessing different memory planes of a memory 有权

    公开(公告)号：US10755755B2

    公开(公告)日：2020-08-25

    申请号：US16109628

    申请日：2018-08-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

    IPC: G06F12/02 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32

    Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

    Apparatuses and methods for concurrently accessing different memory planes of a memory
    8.
    发明授权
    Apparatuses and methods for concurrently accessing different memory planes of a memory 有权

    公开(公告)号：US11462250B2

    公开(公告)日：2022-10-04

    申请号：US16986032

    申请日：2020-08-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

    IPC: G06F3/06 ,  G11C7/22 ,  G11C16/26 ,  G11C16/32

    Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY
    9.
    发明申请
    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY 有权

    公开(公告)号：US20210090623A1

    公开(公告)日：2021-03-25

    申请号：US16986032

    申请日：2020-08-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Violante Moschiano ,  Michele Incarnati ,  Luca de Santis

    IPC: G11C7/22 ,  G11C16/26 ,  G11C16/32

    Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY
    10.
    发明申请
    APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY 审中-公开

    公开(公告)号：US20170270983A1

    公开(公告)日：2017-09-21

    申请号：US15614072

    申请日：2017-06-05

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Theodore T. Pekny ,  Jae-Kwan Park ,  Viloante Moschiano ,  Michele Incarnati ,  Luca de Santis

    IPC: G11C7/22 ,  G11C16/26 ,  G11C16/32

    CPC classification number: G11C7/22 ,  G11C16/26 ,  G11C16/32 ,  G11C2207/2209

    Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

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