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1.发明申请公开(公告)号：US20180366167A1
公开(公告)日：2018-12-20
申请号：US16109628
申请日：2018-08-22
摘要： Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).
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2.发明申请公开(公告)号：US20180197583A1
公开(公告)日：2018-07-12
申请号：US15910375
申请日：2018-03-02
发明人： Jae-Kwan Park
CPC分类号： G11C7/02 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3427
摘要： Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.
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公开(公告)号：US09443610B1
公开(公告)日：2016-09-13
申请号：US14730372
申请日：2015-06-04
发明人： Feng Pan , Shigekazu Yamada , Allahyar Vahidimowlavi , Jae-Kwan Park , Cairong Hu , Kalyan Kavalipurapu
CPC分类号： G11C29/025 , G01R31/025 , G11C16/0483 , G11C2029/1202 , G11C2029/5006
摘要： A system includes a first switch, an amplifier, a second switch, and a capacitor. The first switch is electrically coupled between a first reference voltage and a node. The amplifier has a first input, a second input, and an output, the amplifier to receive a second reference voltage on the first input and a sample voltage on the second input. The second switch is electrically coupled between the output of the amplifier and the second input of the amplifier. The capacitor is electrically coupled between the second input of the amplifier and the node. The first switch and the second switch are closed to initialize the node to the first reference voltage and to initialize the amplifier in unity-gain configuration. The first switch and the second switch are opened to detect a leakage current by sensing a change in the sample voltage.
摘要翻译： 系统包括第一开关，放大器，第二开关和电容器。 第一开关电耦合在第一参考电压和节点之间。 放大器具有第一输入端，第二输入端和输出端，放大器用于在第一输入端接收第二参考电压，并在第二输入端接收采样电压。 第二开关电耦合在放大器的输出端和放大器的第二输入端之间。 电容器电耦合在放大器的第二输入端和节点之间。 关闭第一开关和第二开关以将节点初始化为第一参考电压并以单位增益配置初始化放大器。 打开第一开关和第二开关，通过感测样品电压的变化来检测泄漏电流。
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4.发明授权Apparatuses and methods for comparing a current representative of a number of failing memory cells 有权用于比较多个故障存储器单元的当前代表的装置和方法公开(公告)号：US09349420B2
公开(公告)日：2016-05-24
申请号：US14494808
申请日：2014-09-24
发明人： Jae-Kwan Park
CPC分类号： G06F11/079 , G06F11/0727 , G06F11/0751 , G11C7/062 , G11C7/065 , G11C7/1057 , G11C7/1063 , G11C29/24 , G11C2207/063
摘要： Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.
摘要翻译： 提供了用于比较表示一组存储器单元的故障存储器单元的数量的感测电流和表示参考数量的故障存储单元的参考电流的装置和方法。 一种这样的装置包括被配置为接收感测电流并接收参考电流的比较器。 比较器包括被配置为缓冲感测电流的感测电流缓冲器，并且比较器还被配置为提供具有指示比较结果的逻辑电平的输出信号。
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5.发明申请APPARATUSES AND METHODS FOR CONCURRENTLY ACCESSING DIFFERENT MEMORY PLANES OF A MEMORY 有权用于同时访问存储器的不同存储器的设备和方法公开(公告)号：US20160048343A1
公开(公告)日：2016-02-18
申请号：US14461152
申请日：2014-08-15
IPC分类号： G06F3/06
CPC分类号： G11C7/22 , G11C16/26 , G11C16/32 , G11C2207/2209
摘要： Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).
摘要翻译： 本文公开了用于对不同存储器平面执行并发存储器访问操作的装置和方法。 示例性装置可以包括具有多个存储器平面的存储器阵列。 多个存储器平面中的每一个包括多个存储单元。 该装置还可以包括被配置为接收一组存储器命令和地址对的控制器。 该组存储器命令和地址对的每个存储器命令和地址对可以与多个存储器平面中的相应存储器平面相关联。 内部控制器可以被配置为与存储器命令和地址组组的存储器命令组和地址对组中的每个存储器命令和地址对相关联地执行存储器访问操作，而不管与组的对相关联的页面类型（ 例如，即使两个或多个存储器命令和地址对可以与不同的页面类型相关联）。
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6.发明授权公开(公告)号：US10318372B2
公开(公告)日：2019-06-11
申请号：US16148947
申请日：2018-10-01
发明人： Jae-Kwan Park
摘要： Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.
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7.发明授权公开(公告)号：US10095574B2
公开(公告)日：2018-10-09
申请号：US15840610
申请日：2017-12-13
发明人： Jae-Kwan Park
摘要： Apparatuses and methods for comparing a sense current representative of a number of failing memory cells of a group of memory cells and a reference current representative of a reference number of failing memory cells is provided. One such apparatus includes a comparator configured to receive the sense current and to receive the reference current. The comparator includes a sense current buffer configured to buffer the sense current and the comparator is further configured to provide an output signal having a logic level indicative of a result of the comparison.
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公开(公告)号：US11462250B2
公开(公告)日：2022-10-04
申请号：US16986032
申请日：2020-08-05
摘要： Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).
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公开(公告)号：US20210090623A1
公开(公告)日：2021-03-25
申请号：US16986032
申请日：2020-08-05
摘要： Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).
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10.发明授权公开(公告)号：US09947375B2
公开(公告)日：2018-04-17
申请号：US15610281
申请日：2017-05-31
发明人： Jae-Kwan Park
CPC分类号： G11C7/02 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3427
摘要： Apparatuses and methods for providing a program voltage responsive to a voltage determination are described. An example apparatus includes a memory array comprising a plurality of access lines. The example apparatus further includes a memory access circuit coupled to the memory array. The memory access circuit is configured to, during a memory program operation, provide an inhibit voltage to the plurality of access lines. The memory access circuit is further configured to, during the memory program operation, provide a program voltage to a target access line of the plurality of access lines responsive to a determination that an access line of the plurality of access lines has a voltage equal to or greater than a threshold voltage. The threshold voltage is less than the inhibit voltage.
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