公开(公告)号：US20250118365A1

公开(公告)日：2025-04-10

申请号：US18987269

申请日：2024-12-19

Applicant: Micron Technology, Inc.

Inventor： Hong-Yan Chen ,  Priya Vemparala Guruswamy ,  Pamela Castalino ,  Tomoko Ogura Iwasaki

IPC: G11C11/56 ,  G11C16/08

Abstract: Control logic in a memory device causes a programming pulse to be applied to a set of wordlines, where the programming pulse causes a set of electrons to be injected into a first set of gate regions and a second set of gate regions. The control logic executes a first erase sub-operation on a first subset of the set of wordlines to remove a first subset of the set of electrons from the first set of gate regions. The control logic executes a second erase sub-operation on a second subset of the set of wordlines to remove a second subset of the set of electrons from the second set of gate regions.

公开(公告)号：US12211548B2

公开(公告)日：2025-01-28

申请号：US18085986

申请日：2022-12-21

Applicant: Micron Technology, Inc.

Inventor： Hong-Yan Chen ,  Priya Vemparala Guruswamy ,  Pamela Castalino ,  Tomoko Ogura Iwasaki

IPC: G11C11/00 ,  G11C11/56 ,  G11C16/08

Abstract: Control logic in a memory device cause a programming pulse to be applied to a set of wordlines including a first set of even-numbered wordlines corresponding to a first set of memory cells to be erased and a second set of odd-numbered wordlines corresponding to a second set of memory cells to be erased, where a set of electrons are injected into a first set of gate regions, a second set of gate regions, and a set of inter-cell regions of a charge trap (CT) layer of the memory device. The control logic executes a first erase cycle on the first set of even-numbered wordlines to remove a first subset of electrons from the first set of gate regions corresponding to the first set of even-numbered wordlines. The control logic executes a second erase cycle on the second set of odd-numbered wordlines to remove a second subset of electrons from the second set of gate regions corresponding to the second set of even-numbered wordlines.

公开(公告)号：US20240071531A1

公开(公告)日：2024-02-29

申请号：US18239193

申请日：2023-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tomoko Ogura Iwasaki ,  Hong-Yan Chen ,  Pamela Castalino ,  Priya Vemparala Guruswamy ,  Jun Xu ,  Gianluca Nicosia ,  Ji-Hye Gale Shin

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12

CPC classification number: G11C16/3459 ,  G11C16/0433 ,  G11C16/102 ,  G11C16/12

Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a target level based on a compensation value of a program command. The controller is further configured to sense a threshold voltage of the selected memory cell. The controller is further configured to in response to the compensation value having a first value and the threshold voltage being greater than a first program verify level, inhibit programming of the selected memory cell. The controller is further configured to in response to the compensation value having a second value different from the first value and the threshold voltage being greater than a second program verify level less than the first program verify level, inhibit programming of the selected memory cell.

公开(公告)号：US20230206999A1

公开(公告)日：2023-06-29

申请号：US18085986

申请日：2022-12-21

Applicant: Micron Technology, Inc.

Inventor： Hong-Yan Chen ,  Priya Vemparala Guruswamy ,  Pamela Castalino ,  Tomoko Ogura Iwasaki

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0652

Abstract: Control logic in a memory device cause a programming pulse to be applied to a set of wordlines including a first set of even-numbered wordlines corresponding to a first set of memory cells to be erased and a second set of odd-numbered wordlines corresponding to a second set of memory cells to be erased, where a set of electrons are injected into a first set of gate regions, a second set of gate regions, and a set of inter-cell regions of a charge trap (CT) layer of the memory device. The control logic executes a first erase cycle on the first set of even-numbered wordlines to remove a first subset of electrons from the first set of gate regions corresponding to the first set of even-numbered wordlines. The control logic executes a second erase cycle on the second set of odd-numbered wordlines to remove a second subset of electrons from the second set of gate regions corresponding to the second set of even-numbered wordlines.