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公开(公告)号：US12211548B2
公开(公告)日：2025-01-28
申请号：US18085986
申请日：2022-12-21
Applicant: Micron Technology, Inc.
Inventor： Hong-Yan Chen , Priya Vemparala Guruswamy , Pamela Castalino , Tomoko Ogura Iwasaki
Abstract: Control logic in a memory device cause a programming pulse to be applied to a set of wordlines including a first set of even-numbered wordlines corresponding to a first set of memory cells to be erased and a second set of odd-numbered wordlines corresponding to a second set of memory cells to be erased, where a set of electrons are injected into a first set of gate regions, a second set of gate regions, and a set of inter-cell regions of a charge trap (CT) layer of the memory device. The control logic executes a first erase cycle on the first set of even-numbered wordlines to remove a first subset of electrons from the first set of gate regions corresponding to the first set of even-numbered wordlines. The control logic executes a second erase cycle on the second set of odd-numbered wordlines to remove a second subset of electrons from the second set of gate regions corresponding to the second set of even-numbered wordlines.
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公开(公告)号：US20240071531A1
公开(公告)日：2024-02-29
申请号：US18239193
申请日：2023-08-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tomoko Ogura Iwasaki , Hong-Yan Chen , Pamela Castalino , Priya Vemparala Guruswamy , Jun Xu , Gianluca Nicosia , Ji-Hye Gale Shin
CPC classification number: G11C16/3459 , G11C16/0433 , G11C16/102 , G11C16/12
Abstract: A memory device includes an array of memory cells and a controller configured to access the array of memory cells to program a selected memory cell of the array of memory cells to a target level based on a compensation value of a program command. The controller is further configured to sense a threshold voltage of the selected memory cell. The controller is further configured to in response to the compensation value having a first value and the threshold voltage being greater than a first program verify level, inhibit programming of the selected memory cell. The controller is further configured to in response to the compensation value having a second value different from the first value and the threshold voltage being greater than a second program verify level less than the first program verify level, inhibit programming of the selected memory cell.
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公开(公告)号：US20240071530A1
公开(公告)日：2024-02-29
申请号：US18233420
申请日：2023-08-14
Applicant: Micron Technology, Inc.
Inventor： Ching-Huang Lu , Hong-Yan Chen , Yingda Dong
CPC classification number: G11C16/3459 , G11C16/08 , G11C16/102
Abstract: A program operation is initiated to program a set of target memory cells of a target wordline of a memory device to a target programming level. During a program verify operation of the program operation, a program verify voltage level is caused to be applied to the target wordline to verify programming of the set of target memory cells. A pass through read voltage level associated with the target wordline is identified. During the program verify operation, a pass through voltage level is caused to be applied to at least one of a first wordline or a second wordline, wherein the pass through read voltage level is the read voltage level reduced by an offset value.
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4.发明公开公开(公告)号：US20230206999A1
公开(公告)日：2023-06-29
申请号：US18085986
申请日：2022-12-21
Applicant: Micron Technology, Inc.
Inventor： Hong-Yan Chen , Priya Vemparala Guruswamy , Pamela Castalino , Tomoko Ogura Iwasaki
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/0679 , G06F3/0652
Abstract: Control logic in a memory device cause a programming pulse to be applied to a set of wordlines including a first set of even-numbered wordlines corresponding to a first set of memory cells to be erased and a second set of odd-numbered wordlines corresponding to a second set of memory cells to be erased, where a set of electrons are injected into a first set of gate regions, a second set of gate regions, and a set of inter-cell regions of a charge trap (CT) layer of the memory device. The control logic executes a first erase cycle on the first set of even-numbered wordlines to remove a first subset of electrons from the first set of gate regions corresponding to the first set of even-numbered wordlines. The control logic executes a second erase cycle on the second set of odd-numbered wordlines to remove a second subset of electrons from the second set of gate regions corresponding to the second set of even-numbered wordlines.
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公开(公告)号：US11670372B2
公开(公告)日：2023-06-06
申请号：US17452505
申请日：2021-10-27
Applicant: Micron Technology, Inc.
Inventor： Hong-Yan Chen , Yingda Dong
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/10 , G11C16/3459 , G11C11/5621 , G11C11/5671
Abstract: Control logic in a memory device initiates, subsequent to a program verify phase of a program operation, a new program operation on the memory array, the new program operation comprising a pre-boosting phase occurring prior to a program phase. The control logic causing one or more positive pre-boosting voltages to be applied to corresponding subsets of a plurality of word lines of a block of the memory array during the pre-boosting phase and causes the one or more positive pre-boosting voltages to be ramped down to a ground voltage during the pre-boosting phase in a designated order based on a location of the corresponding subsets of the plurality of word lines to which the one or more positive pre-boosting voltages were applied.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20220189565A1
公开(公告)日：2022-06-16
申请号：US17689862
申请日：2022-03-08
Applicant: Micron Technology, Inc.
Inventor： Hong-Yan Chen , Yingda Dong
Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.
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7.发明授权公开(公告)号：US11749359B2
公开(公告)日：2023-09-05
申请号：US17702525
申请日：2022-03-23
Applicant: Micron Technology, Inc.
Inventor： Hong-Yan Chen , Yingda Dong
CPC classification number: G11C16/3436 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/3413
Abstract: Control logic in a memory device initiates a program operation on the memory device, and causes a program voltage to be applied to a selected wordline of the memory array during a program phase of the program operation. The control logic further causes a select gate drain coupled with a string of memory cells in the memory array to deactivate during a recovery phase after applying the program voltage, wherein the string of memory cells comprises a plurality of memory cells, and wherein each memory cell of the plurality of memory cells is coupled to a corresponding wordline of a plurality of wordlines in the memory array.
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公开(公告)号：US20220277795A1
公开(公告)日：2022-09-01
申请号：US17745852
申请日：2022-05-16
Applicant: Micron Technology, Inc.
Inventor： Kalyan Chakravarthy Kavalipurapu , Tomoko Ogura Iwasaki , Erwin E. Yu , Hong-Yan Chen , Yunfei Xu
Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline.
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9.发明申请公开(公告)号：US20220215890A1
公开(公告)日：2022-07-07
申请号：US17702525
申请日：2022-03-23
Applicant: Micron Technology, Inc.
Inventor： Hong-Yan Chen , Yingda Dong
Abstract: Control logic in a memory device initiates a program operation on the memory device, and causes a program voltage to be applied to a selected wordline of the memory array during a program phase of the program operation. The control logic further causes a select gate drain coupled with a string of memory cells in the memory array to deactivate during a recovery phase after applying the program voltage, wherein the string of memory cells comprises a plurality of memory cells, and wherein each memory cell of the plurality of memory cells is coupled to a corresponding wordline of a plurality of wordlines in the memory array.
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公开(公告)号：US11335412B2
公开(公告)日：2022-05-17
申请号：US16991836
申请日：2020-08-12
Applicant: Micron Technology, Inc.
Inventor： Kalyan Chakravarthy Kavalipurapu , Tomoko Ogura Iwasaki , Erwin E. Yu , Hong-Yan Chen , Yunfei Xu
Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline by an amount equal to a step down interval.
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