Setting an initial erase voltage using feedback from previous operations

    公开(公告)号:US11443812B2

    公开(公告)日:2022-09-13

    申请号:US17127358

    申请日:2020-12-18

    Abstract: A method is described that includes performing a first erase operation on a set of memory cells of a memory device using an erase voltage, which is set to a first voltage value and adjusting the erase voltage to a second voltage value based on feedback from performance of at least the first erase operation. The method further includes performing a second erase operation on the set of memory cells using the erase voltage, which is set to the second voltage value. In this configuration, the erase voltage set to the second voltage value is an initial voltage applied to the set of memory cells to perform erase operations such that each subsequent erase operation on the set of memory cells following the first erase operation uses an erase voltage that is equal to or greater than the second voltage value when erasing the first set of memory cells.

    Memory system failure detection and self recovery of memory dice

    公开(公告)号:US12229024B2

    公开(公告)日:2025-02-18

    申请号:US18608652

    申请日:2024-03-18

    Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

    Dynamic prioritization of selector V

    公开(公告)号:US12106813B2

    公开(公告)日:2024-10-01

    申请号:US17733460

    申请日:2022-04-29

    CPC classification number: G11C29/02 G06F11/073 G11C29/006 G11C2029/0403

    Abstract: Prioritization of VT scans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of VT scans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.

    MANAGING TRAP-UP IN A MEMORY SYSTEM
    9.
    发明公开

    公开(公告)号:US20240233842A1

    公开(公告)日:2024-07-11

    申请号:US18393354

    申请日:2023-12-21

    CPC classification number: G11C16/3495 G11C16/08 G11C16/28 G11C16/3404

    Abstract: Methods, systems, and devices for managing trap-up in a memory system are described. A request to erase a block of a memory device may be received. Based on the request, a scan operation for determining whether a threshold voltage distribution for a dummy word line associated with the block satisfies one or more criteria may be performed. Based on the scan operation, whether to perform one or more program and erase cycles on the block using a first voltage level for a de-biasing operation of a program and erase (P/E) cycle may be determined. The first voltage level may be lower than a second voltage level for one or more prior de-biasing operations of one or more prior P/E cycles performed on the block. The block of memory may be managed based on whether the P/E cycling with the debiasing operation having the voltage level is performed.

    MEMORY SYSTEM FAILURE DETECTION AND SELF RECOVERY OF MEMORY DICE

    公开(公告)号:US20240220375A1

    公开(公告)日:2024-07-04

    申请号:US18608652

    申请日:2024-03-18

    CPC classification number: G06F11/1471 G06F9/30098 G06F11/1469

    Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.

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