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公开(公告)号:US20250046390A1
公开(公告)日:2025-02-06
申请号:US18774447
申请日:2024-07-16
Applicant: MICRON TECHNOLOGY, INC.
Inventor: Fulvio Rori , Pitamber Shukla , Chiara Cerafogli , Erasmo Jose B. Vargas
IPC: G11C29/12
Abstract: A methods and system directed to a wordline ramp rate monitor for early detection of defect activation are disclosed. A memory access directed to a wordline is initiated. Based on an applied ramping voltage, a ramp rate of the wordline is determined. Responsive to determining that the ramp rate satisfied a defect condition, the memory access operation is aborted.
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公开(公告)号:US12153490B2
公开(公告)日:2024-11-26
申请号:US17566921
申请日:2021-12-31
Applicant: Micron Technology, Inc.
Inventor: Priya Venkataraman , Pitamber Shukla , Vipul Patel , Scott A. Stoller
Abstract: Read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. In response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. The page of memory can be read with the respective calibrated read level per sector. The calibrated read levels can be stored.
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公开(公告)号:US20240248616A1
公开(公告)日:2024-07-25
申请号:US18624657
申请日:2024-04-02
Applicant: Micron Technology, Inc.
Inventor: Sandeep Reddy Kadasani , Pitamber Shukla , Scott Anthony Stoller , Niccolo' Righetti
IPC: G06F3/06
CPC classification number: G06F3/0619 , G06F3/064 , G06F3/0653 , G06F3/0688
Abstract: A set of threshold voltage distribution width measurements are obtained for a block in a memory device. An endurance estimate is determined for the block based on the threshold voltage distribution width measurements. The endurance estimate comprises an indication of an estimated number of program/erase cycles during which data can be reliably stored by the block. One or more parameters of the block are managed based on the endurance estimate.
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公开(公告)号:US20230197157A1
公开(公告)日:2023-06-22
申请号:US17741189
申请日:2022-05-10
Applicant: Micron Technology, Inc.
Inventor: Sandeep Kadasani , Pitamber Shukla , Scott A. Stoller , Renato Padilla , Chi Ming Chu
CPC classification number: G11C16/08 , G11C16/30 , G11C16/3495
Abstract: A method includes determining, for a set of memory cells of a word line group, a parameter corresponding to a quality of the set of memory cells of the word line group and determining, for the set of memory cells, a range of voltage offset values corresponding to the parameter. The method can further include determining a voltage offset to be applied to the set of memory cells of the word line group based on the parameter or the range of voltage offset values, or both and applying a signal corresponding to the determined voltage offset to the set of memory cells of the word line group.
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公开(公告)号:US11443812B2
公开(公告)日:2022-09-13
申请号:US17127358
申请日:2020-12-18
Applicant: Micron Technology, Inc.
Inventor: Scott A. Stoller , Pitamber Shukla , Priya Venkataraman , Giuseppina Puzzilli , Niccolo′ Righetti
Abstract: A method is described that includes performing a first erase operation on a set of memory cells of a memory device using an erase voltage, which is set to a first voltage value and adjusting the erase voltage to a second voltage value based on feedback from performance of at least the first erase operation. The method further includes performing a second erase operation on the set of memory cells using the erase voltage, which is set to the second voltage value. In this configuration, the erase voltage set to the second voltage value is an initial voltage applied to the set of memory cells to perform erase operations such that each subsequent erase operation on the set of memory cells following the first erase operation uses an erase voltage that is equal to or greater than the second voltage value when erasing the first set of memory cells.
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公开(公告)号:US20250086058A1
公开(公告)日:2025-03-13
申请号:US18954008
申请日:2024-11-20
Applicant: Micron Technology, Inc.
Inventor: Priya Venkataraman , Pitamber Shukla , Vipul Patel , Scott A. Stoller
Abstract: Read calibration by sector of memory can include reading a page of memory, having more than one sector, with a read level, such as a default read level. In response to an error, such as an uncorrectable error correction code read result, the respective read level can be calibrated for each sector to yield a respective calibrated read level per sector. The page of memory can be read with the respective calibrated read level per sector. The calibrated read levels can be stored.
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公开(公告)号:US12229024B2
公开(公告)日:2025-02-18
申请号:US18608652
申请日:2024-03-18
Applicant: Micron Technology, Inc.
Inventor: Robert Mason , Scott A. Stoller , Pitamber Shukla , Kenneth W. Marr , Chi Ming Chu , Hossein Afkhami
Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.
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公开(公告)号:US12106813B2
公开(公告)日:2024-10-01
申请号:US17733460
申请日:2022-04-29
Applicant: Micron Technology, Inc.
Inventor: Pitamber Shukla , Avinash Rajagiri , Devin Batutis
CPC classification number: G11C29/02 , G06F11/073 , G11C29/006 , G11C2029/0403
Abstract: Prioritization of VT scans can be performed using particular select gates of a memory device or memory sub-system in the absence of performing such select gate scan operations on all of the select gates of an entire memory die or of all the memory dice of a memory device or memory sub-system. A method for such prioritization of VT scans includes determining quality characteristics of a memory die and altering a threshold voltage applied to the memory die in performance of a select gate scan operation based, at least in part, on the determined quality characteristics of the memory die. Such methods can further include performing the select gate scan operation by applying signaling having the altered threshold voltage to a select gate of the memory die.
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公开(公告)号:US20240233842A1
公开(公告)日:2024-07-11
申请号:US18393354
申请日:2023-12-21
Applicant: Micron Technology, Inc.
Inventor: Pitamber Shukla , Chi Ming W. Chu , Avinash Rajagiri , Ching-Huang Lu , Kenneth W. Marr
CPC classification number: G11C16/3495 , G11C16/08 , G11C16/28 , G11C16/3404
Abstract: Methods, systems, and devices for managing trap-up in a memory system are described. A request to erase a block of a memory device may be received. Based on the request, a scan operation for determining whether a threshold voltage distribution for a dummy word line associated with the block satisfies one or more criteria may be performed. Based on the scan operation, whether to perform one or more program and erase cycles on the block using a first voltage level for a de-biasing operation of a program and erase (P/E) cycle may be determined. The first voltage level may be lower than a second voltage level for one or more prior de-biasing operations of one or more prior P/E cycles performed on the block. The block of memory may be managed based on whether the P/E cycling with the debiasing operation having the voltage level is performed.
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公开(公告)号:US20240220375A1
公开(公告)日:2024-07-04
申请号:US18608652
申请日:2024-03-18
Applicant: Micron Technology, Inc.
Inventor: Robert Mason , Scott A. Stoller , Pitamber Shukla , Kenneth W. Marr , Chi Ming Chu , Hossein Afkhami
CPC classification number: G06F11/1471 , G06F9/30098 , G06F11/1469
Abstract: Exemplary methods, apparatuses, and systems including memory self-recovery management to correct failures due to soft-error rate events. The self-recovery manager detects a failure of a memory device. The self-recovery manager retrieves a set of register values from the memory device. The self-recovery manager stores the set of register values from the memory device. The self-recovery manager issues a reset command to the memory device, the reset command including generating a re-initialized set of register values. The self-recovery manager compares the set of register values with the re-initialized set of register values. The self-recovery manager triggering a self-recovery attempt using the comparison of the set of register values with the re-initialized set of register values.
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