公开(公告)号：US20250077077A1

公开(公告)日：2025-03-06

申请号：US18830454

申请日：2024-09-10

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Giuseppe Cariello ,  Fulvio Rori

IPC: G06F3/06

Abstract: Methods, systems, and devices for suspending operations of a memory system are described. A memory system may be configured to perform a write operation to store data in a nonvolatile memory device, where the write operation includes storing information in one or more latches associated with the nonvolatile memory device; receive a suspend command to suspend performance of the write operation based on a request to perform a read operation associated with a higher-priority than the write operation; suspend the performance of the write operation based on receiving the suspend command; transmit the information stored in the one or more latches associated with the nonvolatile memory device to a host system based on suspending the performance of the write operation; and perform the read operation based at least in part on transmitting the information to the host system.

公开(公告)号：US12099748B2

公开(公告)日：2024-09-24

申请号：US17373301

申请日：2021-07-12

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Fulvio Rori ,  Jonathan W Oh ,  Giuseppe Cariello

IPC: G06F3/06 ,  G06F11/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/1068 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C29/52

Abstract: Devices and techniques for NAND temperature-aware operations are disclosed herein. A device controller can receive a command to write data to a component in the device. A temperature corresponding to the component can be obtained in response to receiving the command. The command can be executed by the controller to write data to the component. Executing the command can include writing the temperature into a management portion of the device that is separate from a user portion of the device to which the data is written.

公开(公告)号：US20240231702A1

公开(公告)日：2024-07-11

申请号：US18542388

申请日：2023-12-15

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Fulvio Rori

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and devices for multiplane data transfer commands are described. Implementations may provide a modified transfer command to leverage a sequential nature of a read operation. For example, a memory system may determine to read data stored across a set of planes of a non-volatile memory device and a sequence of the planes may be known. The memory system may issue a transfer command to a controller of the non-volatile memory device that supports automatic switching from one plane to the next in transferring data from the set of planes to a controller of the memory system. As a result, one transfer command may be issued by the memory system controller to transfer the data from the set of planes, for example, rather than one transfer command per plane.

公开(公告)号：US11836373B2

公开(公告)日：2023-12-05

申请号：US17166855

申请日：2021-02-03

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Fulvio Rori

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

CPC classification number: G06F3/0652 ,  G06F3/0619 ,  G06F3/0679 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/0483 ,  G11C16/08

Abstract: Apparatus and methods are disclosed, including receiving an indication to selectively erase first data stored on a first page of a first subset of a group of multi-level memory cells of the storage system, each multi-level memory cell comprising multiple pages and providing, in response the indication to selectively erase the first data, at least one soft erase pulse to the first page of memory cells associated with the first data to induce distribution overlap across different bit levels of the first page of the group of multi-level memory cell.

公开(公告)号：US20220270677A1

公开(公告)日：2022-08-25

申请号：US17691684

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Jonathan W. Oh ,  Fulvio Rori

IPC: G11C11/56

Abstract: Methods, systems, and devices for programming multi-level memory cells are described. After a first pass, an offset in the form of one or more offset pulses, may be applied to MLCs that are in a state of a higher level. The offset may be applied before or during a first part of a second pass. The offset may move the signals of the cells before the cells are finally programmed so as to avoid potential overlaps between the unprogrammed cells and cells that are programmed to the lower half of the final levels during the second pass. The offset cells may then be further moved to the other levels in the higher half of the final levels.

公开(公告)号：US20220059173A1

公开(公告)日：2022-02-24

申请号：US16996363

申请日：2020-08-18

Applicant: Micron Technology, Inc.

Inventor： Shannon Marissa Hansen ,  Fulvio Rori ,  Andrea D'Alessandro ,  Jason Lee Nevill ,  Chiara Cerafogli

IPC: G11C16/20 ,  G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G06F3/06

Abstract: A variety of applications can include a memory device designed to perform sensing of a memory cell of a string of memory cells using a modified shielded bit line sensing operation. The modified shielded bit line sensing operation includes pre-charging a data line corresponding to the string with the string enabled to couple to the data line. The modified shielded bit line sensing operation can be implemented in a hybrid initialization routine for the memory device. The hybrid initialization routine can include a sensing read routine corresponding to an all data line configuration of data lines of the memory device and a modified sensing read routine corresponding to a shielded data line configuration of the data lines with selected strings enabled during pre-charging. A read retry routine associated with the modified sensing read routine can be added to the hybrid initialization routine. Additional devices, systems, and methods are discussed.

公开(公告)号：US11216219B2

公开(公告)日：2022-01-04

申请号：US16871366

申请日：2020-05-11

Applicant: Micron Technology, Inc.

Inventor： Liang Yu ,  John Paul Aglubat ,  Fulvio Rori

IPC: G06F3/00 ,  G06F3/06 ,  G11C7/10 ,  G06F1/14

Abstract: A memory management operation is executed on a plurality of memory dies of a memory sub-system. The memory sub-system determines whether a first measured current level corresponding to execution of the memory management operation satisfies a condition pertaining to a threshold peak current level. The memory sub-system determines whether a second measured current level corresponding to execution of the memory management operation satisfies the condition pertaining to the threshold peak current level. Mask data is generated identifying the first measured current level and the second measured current level. A request is received from a host system to execute the memory management operation. The memory sub-system performs, based on the mask data, a peak current management action during execution of the memory management operation.

公开(公告)号：US11061606B2

公开(公告)日：2021-07-13

申请号：US16023130

申请日：2018-06-29

Applicant: Micron Technology, Inc.

Inventor： Chiara Cerafogli ,  Fulvio Rori ,  Jonathan W Oh ,  Giuseppe Cariello

IPC: G06F3/06 ,  G11C16/26 ,  G11C29/52 ,  G11C16/04 ,  G11C16/10 ,  G06F11/10 ,  G06F16/11 ,  G06F16/174

Abstract: Devices and techniques for NAND temperature-aware operations are disclosed herein. A device controller can receive a command to write data to a component in the device. A temperature corresponding to the component can be obtained in response to receiving the command. The command can be executed by the controller to write data to the component. Executing the command can include writing the temperature into a management portion of the device that is separate from a user portion of the device to which the data is written.

公开(公告)号：US10884638B1

公开(公告)日：2021-01-05

申请号：US16452228

申请日：2019-06-25

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Chiara Cerafogli ,  Marco Domenico Tiburzi ,  Fulvio Rori

IPC: G06F3/06

Abstract: The disclosure describes a programmable power management system for NAND Flash devices. In one embodiment, dedicated match logic is provided to store program counters responsible for peak power consumption of one or more NAND Flash dies. Upon detecting that a current program counter equals a stored program counter, a high current enable signal is toggled causing at least one NAND Flash die to suspend operations, thereby reducing peak power consumption of the NAND Flash device.

公开(公告)号：US20200210105A1

公开(公告)日：2020-07-02

申请号：US16235925

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Fulvio Rori ,  Chiara Cerafogli ,  Giuseppe Cariello ,  Jonathan Parry

IPC: G06F3/06

Abstract: Devices and techniques for accelerated memory device trim initialization are described herein. An initialization of a memory device can be started by the memory device. An accelerated trim command can be received at the memory device from a controller. The memory device can refrain from setting a trim in response to receipt of the accelerated trim command. Here, the trim is expected to be set by the controller. The memory device can then complete the initialization after the trim is set by the controller.