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    SEMICONDUCTOR DEVICE HAVING MODE REGISTER
    1.
    发明申请
    SEMICONDUCTOR DEVICE HAVING MODE REGISTER 审中-公开

    公开(公告)号：US20200082869A1

    公开(公告)日：2020-03-12

    申请号：US16685914

    申请日：2019-11-15

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Takayuki Miyamoto

    IPC: G11C11/4076 ,  G11C7/22 ,  G06F5/06 ,  G11C11/4096

    Abstract: Disclosed herein is an apparatus that includes a first circuit that activates first and second timing signals in response to a first command and activates the second timing signal in response to a second command, a second circuit that amplifies a first data read out from a first memory area in response to the first command in synchronization with the first timing signal, and a third circuit that outputs one of the first data output from the second circuit and a second data read out from a second memory area in response to the second command, in synchronization with the second timing signal.

    PROCESSING OF UNASSIGNED ROW ADDRESS IN A MEMORY
    3.
    发明申请
    PROCESSING OF UNASSIGNED ROW ADDRESS IN A MEMORY 有权

    公开(公告)号：US20210398585A1

    公开(公告)日：2021-12-23

    申请号：US16904004

    申请日：2020-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Takayuki Miyamoto ,  Satoshi Yamanaka

    IPC: G11C11/408 ,  G11C11/4096 ,  G11C11/4093 ,  G11C11/4094

    Abstract: Semiconductor devices that include circuitry to mitigate unstable or metastable states in logic circuits in response to receipt of an unassigned row address. The semiconductor device may include one or more logic circuits that are configured to adjust particular address-based control signals to mitigate processing based on the unassigned row address. For example, the one or more logic circuits may override processing of the unassigned row address to provide control signals that correspond to an assigned row address, which may allow the semiconductor device to operate in a known state, rather than performing operations based on an unassigned row address.

    APPARATUSES AND METHODS FOR REDUCED POWER COMMAND SHIFTER
    6.
    发明申请
    APPARATUSES AND METHODS FOR REDUCED POWER COMMAND SHIFTER 有权

    公开(公告)号：US20250140304A1

    公开(公告)日：2025-05-01

    申请号：US18774032

    申请日：2024-07-16

    Applicant: Micron Technology, Inc.

    Inventor： Yukimi Morimoto ,  Takayuki Miyamoto ,  Atsuko Momma

    IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    Abstract: A memory device includes a command shifter which includes a latch array with latches coupled in series. After receiving a command the command passes through the latch array and a ready pulse is provided when the command exits the array. The latch array is divided into portions (e.g., rows) with each row receiving its own clock signal from a respective clock circuit. Each clock signal is toggling while the command is within that row of the latch array or about to enter that row. For example, when the command is within N latches of the end of the previous row of the latch array or when a setting and command signal indicates the command is about to initially enter the array in that row.

    Processing of unassigned row address in a memory
    8.
    发明授权
    Processing of unassigned row address in a memory 有权

    公开(公告)号：US11417388B2

    公开(公告)日：2022-08-16

    申请号：US16904004

    申请日：2020-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Takayuki Miyamoto ,  Satoshi Yamanaka

    IPC: G11C11/408 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4093

    Abstract: Semiconductor devices that include circuitry to mitigate unstable or metastable states in logic circuits in response to receipt of an unassigned row address. The semiconductor device may include one or more logic circuits that are configured to adjust particular address-based control signals to mitigate processing based on the unassigned row address. For example, the one or more logic circuits may override processing of the unassigned row address to provide control signals that correspond to an assigned row address, which may allow the semiconductor device to operate in a known state, rather than performing operations based on an unassigned row address.

    Burst clock control based on partial command decoding in a memory device
    9.
    发明授权
    Burst clock control based on partial command decoding in a memory device 有权

    公开(公告)号：US11211103B1

    公开(公告)日：2021-12-28

    申请号：US16996025

    申请日：2020-08-18

    Applicant: Micron Technology, Inc.

    Inventor： Kallol Mazumder ,  Takayuki Miyamoto

    IPC: G11C7/22 ,  G06F13/28 ,  G11C7/10 ,  G06F1/12 ,  G06F1/08

    Abstract: Devices and methods include a command input configured to receive a command for a memory device. Second stage wakeup circuitry configured to receive a portion of the command and output an indication of whether the command is a non-burst command based on the portion. Clock gating circuitry is configured to receive an input clock and a wake signal. The clock gating circuitry is also configured to output an internal clock based at least in part on a pulse of the received wake signal. The clock gating circuitry also is configured to maintain the output of the internal clock for a duration based on the indication with the duration being shorter when the indication indicates that the command is a non-burst command.

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