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    Timing adjustment for data input/output buffer circuits
    1.
    发明授权
    Timing adjustment for data input/output buffer circuits 有权

    公开(公告)号：US12073868B2

    公开(公告)日：2024-08-27

    申请号：US17834754

    申请日：2022-06-07

    Applicant: Micron Technology, Inc.

    Inventor： Noriaki Mochida

    IPC: G11C11/4076 ,  G11C11/4093

    CPC classification number: G11C11/4076 ,  G11C11/4093

    Abstract: Apparatuses including a loopback circuit are disclosed. An example apparatus according to the disclosure includes a plurality of input signal receivers and a loopback circuit coupled to the plurality of input signal receivers. The loopback circuit includes a signal multiplexer and a selector. The signal multiplexer provides an input signal received at one input receiver of the plurality of input receivers as a selected signal. The selector coupled to the signal multiplexer provides a loopback signal based on the selected signal and an alleviation signal that transitions between two different states, periodically.

    TIMING CONTROL CIRCUIT SHARED BY A PLURALITY OF BANKS
    4.
    发明申请
    TIMING CONTROL CIRCUIT SHARED BY A PLURALITY OF BANKS 审中-公开

    公开(公告)号：US20190156880A1

    公开(公告)日：2019-05-23

    申请号：US16257867

    申请日：2019-01-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Noriaki Mochida

    IPC: G11C11/4091 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4076

    Abstract: Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.

    TIMING CONTROL CIRCUIT SHARED BY A PLURALITY OF BANKS
    5.
    发明申请
    TIMING CONTROL CIRCUIT SHARED BY A PLURALITY OF BANKS 有权
    由多个银行共享的定时控制电路

    公开(公告)号：US20170076778A1

    公开(公告)日：2017-03-16

    申请号：US15245727

    申请日：2016-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Noriaki Mochida

    IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/406 ,  G11C11/4076

    CPC classification number: G11C11/4091 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4094

    Abstract: Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.

    Abstract translation: 描述了用于在半导体器件中提供读出放大器的激活定时的装置和方法。 示例性装置包括：第一存储体，包括响应于第一激活信号使能的至少一个第一读出放大器; 第二存储器组，包括响应于第二激活信号使能的至少一个第二读出放大器; 以及接收控制信号的控制电路。 所述控制电路包括延迟电路，所述延迟电路通过延迟所述控制信号来提供延迟的控制信号;第一读出放大器控制电路，耦合到所述第一延迟电路，并在所述第一存储器组被指定时提供与所述延迟的控制信号相对应的所述第一激活信号 以及耦合到所述延迟电路的第二读出放大器控制电路，并且当指定所述第二存储体时，提供相应于所述延迟控制信号的所述第二激活信号。

    Semiconductor device including subword driver circuit
    6.
    发明授权
    Semiconductor device including subword driver circuit 有权
    半导体器件包括子字驱动电路

    公开(公告)号：US09552866B2

    公开(公告)日：2017-01-24

    申请号：US14642411

    申请日：2015-03-09

    Applicant: Micron Technology, Inc.

    Inventor： Noriaki Mochida

    IPC: G11C5/06 ,  G11C5/14 ,  G11C8/00 ,  G11C11/408 ,  G11C11/4097 ,  G11C8/08

    CPC classification number: G11C11/4085 ,  G11C8/08 ,  G11C11/4097

    Abstract: The present invention is provided with: subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK1 or VKK2 to the subword drivers SWD, and memory cells MC that are selected in the case when the subword line SWL is set to an active potential VPP and are not selected in the case when the subword line SWL is either a negative potential VKK1 or VKK2.

    Abstract translation: 本发明提供：用于驱动子字线SWL的子字驱动器SWD，用于向子字驱动器SWD提供负电位VKK1或VKK2的选择电路，以及在设置子字线SWL的情况下选择的存储器单元MC 到主动电位VPP，并且在子字线SWL是负电位VKK1或VKK2的情况下不被选择。

    Semiconductor device including subword driver circuit
    8.
    发明授权
    Semiconductor device including subword driver circuit 有权

    公开(公告)号：US10332584B2

    公开(公告)日：2019-06-25

    申请号：US15382358

    申请日：2016-12-16

    Applicant: Micron Technology, Inc.

    Inventor： Noriaki Mochida

    IPC: G11C11/408 ,  G11C8/08 ,  G11C11/4097

    Abstract: The present invention is provided with; subword drivers SWD for driving subword lines SWL, a selection circuit for supplying either negative potential VKK1 or VKK2 to the subword drivers SWD, and memory cells MC that are selected in the case when the subword line SWL is set to an active potential VPP and are not selected in the case when the subword line SWL is either a negative potential VKK1 or VKK2.

    Timing control circuit shared by a plurality of banks
    9.
    发明授权
    Timing control circuit shared by a plurality of banks 有权

    公开(公告)号：US10229730B2

    公开(公告)日：2019-03-12

    申请号：US15682775

    申请日：2017-08-22

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Noriaki Mochida

    IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/406 ,  G11C8/12 ,  G11C11/4094

    Abstract: Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.

    Timing control circuit shared by a plurality of banks
    10.
    发明授权
    Timing control circuit shared by a plurality of banks 有权

    公开(公告)号：US09779800B2

    公开(公告)日：2017-10-03

    申请号：US15245727

    申请日：2016-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Noriaki Mochida

    IPC: G11C11/4091 ,  G11C11/408 ,  G11C11/406 ,  G11C11/4076

    CPC classification number: G11C11/4091 ,  G11C8/12 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4094

    Abstract: Apparatuses and methods for providing activation timings of sense amplifiers in a semiconductor device are described. An example apparatus includes: a first memory bank including at least one first sense amplifier that is enabled responsive to a first activation signal; a second memory bank including at least one second sense amplifier that is enabled responsive to a second activation signal; and a control circuit that receives a control signal. The control circuit includes a delay circuit that provides a delayed control signal by delaying the control signal, a first sense amplifier control circuit coupled to the first delay circuit and provides the first activation signal respective to the delayed control signal when the first memory bank is designated, and a second sense amplifier control circuit coupled to the delay circuit and provides the second activation signal respective to the delayed control signal when the second memory bank is designated.

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