公开(公告)号：US12165690B2

公开(公告)日：2024-12-10

申请号：US17849100

申请日：2022-06-24

Applicant: Micron Technology, Inc.

Inventor： John E. Riley ,  Joo-Sang Lee ,  Scott E. Smith

IPC: G11C11/406 ,  G11C11/4074

Abstract: Methods, systems, and devices for adjusting a refresh rate during a self-refresh state are described. A memory system may enter a self-refresh state and execute a first set of refresh operations on a set of rows of memory cells at the memory system according to a first rate. The memory system may determine, based on executing the first set of refresh operations, that a counter associated with the set of refresh operations satisfies a threshold for a second time while the memory system is in the self-refresh state. In response to the counter satisfying the threshold for the second time, a flip-flop circuit at the memory system may modify an output of the flip-flop circuit and the memory system may decrease the rate for executing the refresh operations to a second rate based on the modified output of the flip-flop circuit.

公开(公告)号：US20240176699A1

公开(公告)日：2024-05-30

申请号：US18504234

申请日：2023-11-08

Applicant: Micron Technology, Inc.

Inventor： Sujeet Ayyapureddi ,  Scott E. Smith

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/1016

Abstract: Apparatuses, systems, and methods for enhanced metadata information. The memory array includes a number of column planes and an extra column plane. A memory device is set in an ×4 single-pass operational mode. In this mode, the memory may store a data codeword in a selected ones of the column planes, and metadata may be stored in a non-selected ones of the column planes and in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in the non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

公开(公告)号：US11842985B2

公开(公告)日：2023-12-12

申请号：US17965561

申请日：2022-10-13

Applicant: Micron Technology, Inc.

Inventor： Christian N. Mohr ,  Scott E. Smith

IPC: G01R27/14 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L25/0657 ,  G01R27/14 ,  H01L23/5385

Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.

公开(公告)号：US11687403B2

公开(公告)日：2023-06-27

申请号：US17350099

申请日：2021-06-17

Applicant: Micron Technology, Inc.

Inventor： Aaron Jannusch ,  Brett K. Dodds ,  Debra M. Bell ,  Joshua E. Alzheimer ,  Scott E. Smith

IPC: G11C29/00 ,  G06F11/10

CPC classification number: G06F11/1044 ,  G06F11/102 ,  G06F11/1032

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which a host device may access a group of memory cells (e.g., portion of an array configurable to store ECC parity bits) otherwise reserved for ECC functionality of a memory device. The memory device may include a register to indicate whether its ECC functionality is enabled or disabled. When the register indicates the ECC functionality is disabled, the memory device may increase a storage capacity available to the host device by making the group of memory cells available for user-accessible data. Additionally or alternatively, the memory device may store metadata associated with various operational aspects of the memory device in the group of memory cells. Moreover, the memory device may modify a burst length to accommodate additional information to be stored in or read from the group of memory cells.

公开(公告)号：US11495577B2

公开(公告)日：2022-11-08

申请号：US16894568

申请日：2020-06-05

Applicant: Micron Technology, Inc.

Inventor： Christian N. Mohr ,  Scott E. Smith

IPC: H01L25/065 ,  G01R27/14 ,  H01L23/538

Abstract: Semiconductor devices having through-stack interconnects for facilitating connectivity testing, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor device includes a stack of semiconductor dies and a plurality of through-stack interconnects extending through the stack to electrically couple the semiconductor dies. The interconnects include functional interconnects and at least one test interconnect. The test interconnect is positioned in a portion of the stack more prone to connectivity defects than the functional interconnects. Accordingly, testing the connectivity of the test interconnect can provide an indication of the connectivity of the functional interconnects.

公开(公告)号：US10896703B2

公开(公告)日：2021-01-19

申请号：US16523952

申请日：2019-07-26

Applicant: Micron Technology, Inc.

Inventor： Scott E. Smith ,  Vijayakrishna J. Vankayala

IPC: G11C7/10 ,  G11C7/22 ,  G11C11/408 ,  G11C11/4093

Abstract: A memory device includes: a set of input pads configured to receive from a source external to the memory device one or more input signals and a chip select signal; an operation circuit electrically coupled to the input pads, operation circuit configured to perform operations corresponding to the one or more input signals when the chip select signal is enabled; and an input management circuit electrically coupled to and between the input pads and the operation circuit, the input management circuit configured to control propagation of the one or more input signals based on the chip select signal.

公开(公告)号：US10475488B1

公开(公告)日：2019-11-12

申请号：US15975713

申请日：2018-05-09

Applicant: Micron Technology, Inc.

Inventor： Scott E. Smith ,  Vijayakrishna J. Vankayala

IPC: G11C7/10 ,  G11C11/4093 ,  G11C11/408 ,  G11C7/22

Abstract: A memory device includes: a set of input pads configured to receive from a source external to the memory device one or more input signals and a chip select signal; an operation circuit electrically coupled to the input pads, operation circuit configured to perform operations corresponding to the one or more input signals when the chip select signal is enabled; and an input management circuit electrically coupled to and between the input pads and the operation circuit, the input management circuit configured to control propagation of the one or more input signals based on the chip select signal.

公开(公告)号：US20190333594A1

公开(公告)日：2019-10-31

申请号：US16446848

申请日：2019-06-20

Applicant: Micron Technology, Inc.

Inventor： John E. Riley ,  Girish N. Cherussery ,  Scott E. Smith ,  Yu-Feng Chen

IPC: G11C17/16 ,  G11C29/00 ,  G11C7/10 ,  H01L23/525 ,  G11C11/34

Abstract: An electronic device including: a fuse array including: fuse elements organized along a first direction and a second direction, wherein each fuse element is configured to store information, and a selection circuit configured to provide access to the fuse elements according to positions of the fuse elements along the first direction and the second direction; and a fuse read circuit connected to the fuse array, the fuse read circuit configured to generate a fuse-read output based on reading from one or more of the fuse elements.

公开(公告)号：US20190108869A1

公开(公告)日：2019-04-11

申请号：US16189434

申请日：2018-11-13

Applicant: Micron Technology, Inc.

Inventor： Michael V. Ho ,  Scott E. Smith

IPC: G11C11/4096 ,  G11C11/4094 ,  G11C11/22 ,  G11C11/408

Abstract: Methods, systems, and devices for mitigating line-to-line capacitive coupling in a memory die are described. A device may include multiple drivers configured to both drive latched data and conduct read and write operations. For example, a memory device may contain two or more memory arrays independently coupled to two drivers via two data lines. One data line may be driven strongly to shield a corresponding memory array from effects associated with data line capacitive coupling. An opposing data line may be driven with data pertaining to an access operation of the memory array to which it is coupled. The opposing data line may be driven concurrently or within a small time difference of the other data line.

公开(公告)号：US12271623B2

公开(公告)日：2025-04-08

申请号：US17648513

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Sujeet V. Ayyapureddi ,  Scott E. Smith

IPC: G06F3/06

Abstract: Methods, systems, and devices for metadata implementation for memory devices are described. A memory device may read metadata, transfer the metadata to a buffer, and read information. For example, the memory device may receive a read command from a host device to read information. The memory device may execute a first internal read command to read the metadata associated with the information. Upon reading the metadata, the memory device may store the metadata in the buffer (e.g., one or more latches). Upon determining that a duration has elapsed, the memory device may execute a second internal read command to read the information associated with the metadata. The memory device transmits the information and the metadata to the host device. In some other cases, the memory device may write information, store metadata in a buffer, and write the metadata (e.g., a different order than for read operations).