公开(公告)号：US20170077118A1

公开(公告)日：2017-03-16

申请号：US14854383

申请日：2015-09-15

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： CHENG-HSIEN CHENG ,  CHIH-WEI LEE ,  SHAW-HUNG KU ,  WEN-PIN LU

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/26 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578

摘要： Embodiments of the present invention provide improved three-dimensional memory cells, arrays, devices, and/or the like and associated methods. In one embodiment, a three-dimensional memory cell is provided. The three-dimensional memory cell comprises a first conductive layer; a third conductive layer spaced apart from the first conductive layer; a channel conductive layer connecting the first conductive layer and the third conductive layer to form an opening having internal surfaces; a dielectric layer disposed along the internal surfaces of the opening surrounded by the first conductive layer, the channel conductive layer and the third conductive layer; and a second conductive layer interposed and substantially filling a remaining open portion formed by the dielectric layer. The first conductive layer, the dielectric layer, and the second conductive layer are configured to form a staircase structure.

摘要翻译： 本发明的实施例提供改进的三维存储器单元，阵列，器件和/或类似物以及相关联的方法。 在一个实施例中，提供三维存储单元。 三维存储单元包括第一导电层; 与所述第一导电层间隔开的第三导电层; 连接第一导电层和第三导电层以形成具有内表面的开口的沟道导电层; 沿着由所述第一导电层，所述沟道导电层和所述第三导电层包围的所述开口的内表面设置的电介质层; 以及插入并基本上填充由电介质层形成的剩余开口部分的第二导电层。 第一导电层，电介质层和第二导电层被配置成形成阶梯结构。

公开(公告)号：US20150279468A1

公开(公告)日：2015-10-01

申请号：US14242757

申请日：2014-04-01

申请人： Macronix International Co., Ltd.

发明人： CHIH-WEI LEE ,  TIEN-FAN OU ,  JYUN-SIANG HUANG ,  CHIEN-HUNG LIU

IPC分类号： G11C16/04 ,  H01L29/167 ,  H01L21/265 ,  G11C16/24 ,  H01L23/528 ,  H01L21/768 ,  H01L27/115 ,  G11C16/08

CPC分类号： G11C16/0491 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L27/11568 ,  H01L29/1045 ,  H01L29/167

摘要： An integrated circuit comprises a memory array including diffusion bit lines having composite impurity profiles in a substrate. A plurality of word lines overlies channel regions in the substrate between the diffusion bit lines, with data storage structures such as floating gate structures or dielectric charge trapping structures, at the cross-points. The composite impurity diffusion bit lines provide source/drain terminals on opposing sides of the channel regions that have high conductivity, good depth and steep doping profiles, even with channel region critical dimensions below 50 nanometers.

摘要翻译： 集成电路包括存储器阵列，其包括在衬底中具有复合杂质分布的扩散位线。 多个字线覆盖在扩散位线之间的衬底中的通道区域，在交叉点处具有数据存储结构，例如浮置栅极结构或介电电荷俘获结构。 复合杂质扩散比特线在沟道区的相对侧上提供了具有高导电性，良好深度和陡峭掺杂分布的源极/漏极端子，即使沟道区临界尺寸低于50纳米。