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公开(公告)号：US20200026991A1
公开(公告)日：2020-01-23
申请号：US16224602
申请日：2018-12-18
Applicant: Macronix International Co., Ltd.
Inventor： Yu-Hsuan Lin , Chao-Hung Wang , Ming-Hsiu Lee
Abstract: An in-memory computing device includes a plurality of synaptic layers including a first type of synaptic layer and a second type of synaptic layer. The first type of synaptic layer comprises memory cells of a first type of memory cell and the second type of synaptic layer comprises memory cells of a second type, the first type of memory cell being different than the second type of memory cell. The first and second types of memory cells can be different types of memories, have different structures, different memory materials, and/or different read/write algorithms, any one of which can result in variations in the stability or accuracy of the data stored in the memory cells.
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公开(公告)号：US11853890B2
公开(公告)日：2023-12-26
申请号：US16522986
申请日：2019-07-26
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Chao-Hung Wang , Yu-Hsuan Lin , Ming-Liang Wei , Dai-Ying Lee
Abstract: Provided is an operation method for a memory device, the memory device being used for implementing an Artificial Neural Network (ANN). The operation method includes: reading from the memory device a weight matrix of a current layer of a plurality of layers of the ANN to extract a plurality of neuro values; determining whether to perform calibration; when it is determined to perform calibration, recalculating and updating a mean value and a variance value of the neuro values; and performing batch normalization based on the mean value and the variance value of the neuro values.
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Patent Agency Ranking
3.发明授权公开(公告)号：US10970044B2
公开(公告)日：2021-04-06
申请号：US16407343
申请日：2019-05-09
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ming-Hsiu Lee , Chao-Hung Wang
Abstract: A semiconductor device for performing a sum-of-product computation and an operating method thereof are provided. The semiconductor device includes an inputting circuit, a scaling circuit, a computing memory and an outputting circuit. The inputting circuit is used for receiving a plurality of inputting signals. The inputting signals are voltages or currents. The scaling circuit is connected to the inputting circuit for transforming the inputting signals to be a plurality of compensated signals respectively. The compensated signals are voltages or currents. The computing memory is connected to the scaling circuit. The computing memory includes a plurality of computing cells and the compensated signals are applied to the computing cells respectively. The outputting circuit is connected to the computing memory for reading an outputting signals of the computing cells. The outputting signal is voltage or current.
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公开(公告)号：US10971200B2
公开(公告)日：2021-04-06
申请号：US16154831
申请日：2018-10-09
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Chao-Hung Wang
Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD′.
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5.发明授权公开(公告)号：US10482953B1
公开(公告)日：2019-11-19
申请号：US16103022
申请日：2018-08-14
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Yu-Yu Lin , Feng-Min Lee , Chao-Hung Wang , Po-Hao Tseng , Kai-Chieh Hsu
Abstract: A multi-state memory device includes a first memory element, a second memory element, a first controlling element and a second controlling element. The second memory element has a memory cell structure identical to that of the first memory element and connects to the first memory element in series. The first controlling element is connected to the first memory element either in series or in parallel. The second controlling element has a characteristic value identical to that of the first controlling element and is connected to the second memory element by a connection structure identical to that of the first controlling element. When the first memory element receives a first signal and a second signal through the first controlling element, a first state value and a second state value are generated correspondingly, and the characteristic value is greater than the first state value and less than the second state value.
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公开(公告)号：US11138497B2
公开(公告)日：2021-10-05
申请号：US16224602
申请日：2018-12-18
Applicant: Macronix International Co., Ltd.
Inventor： Yu-Hsuan Lin , Chao-Hung Wang , Ming-Hsiu Lee
Abstract: An in-memory computing device includes a plurality of synaptic layers including a first type of synaptic layer and a second type of synaptic layer. The first type of synaptic layer comprises memory cells of a first type of memory cell and the second type of synaptic layer comprises memory cells of a second type, the first type of memory cell being different than the second type of memory cell. The first and second types of memory cells can be different types of memories, have different structures, different memory materials, and/or different read/write algorithms, any one of which can result in variations in the stability or accuracy of the data stored in the memory cells.
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公开(公告)号：US11594266B2
公开(公告)日：2023-02-28
申请号：US17195712
申请日：2021-03-09
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Yu-Hsuan Lin , Chao-Hung Wang
Abstract: A semiconductor circuit and an operating method for the same are provided. The method includes the following steps. A memory circuit is operated during a first timing to obtain a first memory state signal S1. The memory circuit is operated during a second timing after the first timing to obtain a second memory state signal S2. A difference between the first memory state signal S1 and the second memory state signal S2 is calculated to obtain a state difference signal SD. A calculating is performed to obtain an un-compensated output data signal OD relative with an input data signal ID and the second memory state signal S2. The state difference signal SD and the un-compensated output data signal OD are calculated to obtain a compensated output data signal OD′.
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