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    In-memory computation device
    1.
    发明授权
    In-memory computation device 有权

    公开(公告)号：US12277968B2

    公开(公告)日：2025-04-15

    申请号：US18330369

    申请日：2023-06-07

    Applicant: MACRONIX International Co., Ltd.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee

    IPC: G11C13/00

    Abstract: An in-memory computation device includes multiple computation blocks, a first reference weight block, and an output result generator. The computation blocks have multiple weighting values, receive multiple input signals respectively, and generate multiple computation results. Each of the computation blocks generates each of the computation results according to each of the corresponding input signals and corresponding weighting values. The first reference weight block provides a first reference resistance according to multiple reference weighting values and generates a first reference signal according to the first reference resistance and a read voltage. The output result generator generates multiple output computation results according to the first reference signal and the computation results.

    UNIVERSAL MEMORIES FOR IN-MEMORY COMPUTING
    2.
    发明申请
    UNIVERSAL MEMORIES FOR IN-MEMORY COMPUTING 有权

    公开(公告)号：US20250086443A1

    公开(公告)日：2025-03-13

    申请号：US18464718

    申请日：2023-09-11

    Applicant: Macronix International Co., Ltd.

    Inventor： Feng-Min Lee ,  Po-Hao Tseng ,  Yu-Yu Lin ,  Ming-Hsiu Lee

    IPC: G06N3/063 ,  G11C11/405 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/54

    Abstract: A universal memory device includes an array of universal memory cells. Each universal memory cell includes a write transistor and a read transistor. The write transistor has a gate terminal configured to receive a gate voltage to turn on or off the write transistor, a first terminal configured to receive a write voltage, and a second terminal coupled to a gate terminal of the read transistor. The read transistor includes a charge trap layer at the gate terminal of the read transistor. The charge trap layer is configured to: be unalterable when the first write voltage is applied at the first terminal of the write transistor, and be alterable when the second write voltage is applied at the first terminal of the write transistor to change a threshold voltage of the read transistor. The second write voltage is greater than the first write voltage.

    Memory device for in-memory computing, computing method and computing cell thereof
    3.
    发明授权
    Memory device for in-memory computing, computing method and computing cell thereof 有权

    公开(公告)号：US12057162B2

    公开(公告)日：2024-08-06

    申请号：US17929318

    申请日：2022-09-02

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee

    IPC: G11C16/04 ,  G11C13/00 ,  G11C16/10 ,  H03K19/20

    CPC classification number: G11C13/0002 ,  H03K19/20

    Abstract: An in-memory-computing method for a memory device includes: storing weight values in cascaded computing cells each including first and second computing memory cells, wherein the first computing memory cells are cascaded in series into a first computing memory cell string and the second computing memory cells are cascaded in series into a second computing memory cell string: receiving input values by the first and the second computing memory cell strings; performing a first logic operation on the input values and the weight values by the first computing memory cell string to generate a first logic operation result, and performing a second logic operation on the input values and the weight values by the second computing memory cell string to generate a second logic operation result: and performing a third logic operation on the first and the second logic operation results to generate an output logic operation result.

    Sum-of-products accelerator array
    5.
    发明授权
    Sum-of-products accelerator array 有权

    公开(公告)号：US10719296B2

    公开(公告)日：2020-07-21

    申请号：US15873369

    申请日：2018-01-17

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Feng-Min Lee ,  Yu-Yu Lin

    IPC: G06F7/544 ,  H03K19/17704 ,  G11C16/04 ,  G11C11/54 ,  H01L27/1157 ,  H01L27/11524 ,  H01L45/00

    Abstract: A device for generating sum-of-products data includes an array of variable resistance cells, variable resistance cells in the array each comprising a programmable threshold transistor and a resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells. Control and bias circuitry are coupled to the array, including logic for programming the programmable threshold transistors in the array with thresholds corresponding to values of a weight factor Wmn for the corresponding cell. Input drivers are coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs Xm to rows m. Column drivers are configured to apply currents In to corresponding ones of the n columns of cells. Voltage sensing circuits operatively coupled to the columns of cells.

    Multi-state memory device and method for adjusting memory state characteristics of the same
    6.
    发明授权
    Multi-state memory device and method for adjusting memory state characteristics of the same 有权

    公开(公告)号：US10482953B1

    公开(公告)日：2019-11-19

    申请号：US16103022

    申请日：2018-08-14

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Hsuan Lin ,  Yu-Yu Lin ,  Feng-Min Lee ,  Chao-Hung Wang ,  Po-Hao Tseng ,  Kai-Chieh Hsu

    IPC: G11C11/56 ,  H01L27/22 ,  H01L27/24

    Abstract: A multi-state memory device includes a first memory element, a second memory element, a first controlling element and a second controlling element. The second memory element has a memory cell structure identical to that of the first memory element and connects to the first memory element in series. The first controlling element is connected to the first memory element either in series or in parallel. The second controlling element has a characteristic value identical to that of the first controlling element and is connected to the second memory element by a connection structure identical to that of the first controlling element. When the first memory element receives a first signal and a second signal through the first controlling element, a first state value and a second state value are generated correspondingly, and the characteristic value is greater than the first state value and less than the second state value.

    METHOD FOR MANUFACTURING A RESISTIVE RANDOM ACCESS MEMORY DEVICE
    10.
    发明申请
    METHOD FOR MANUFACTURING A RESISTIVE RANDOM ACCESS MEMORY DEVICE 有权
    制造电阻随机存取存储器件的方法

    公开(公告)号：US20170047514A1

    公开(公告)日：2017-02-16

    申请号：US14825209

    申请日：2015-08-13

    Applicant: MACRONIX INTERNATIONAL CO., LTD.

    Inventor： Yu-Yu Lin ,  Feng-Min Lee

    IPC: H01L45/00

    CPC classification number: H01L45/1633 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

    Abstract: A method for manufacturing a resistive memory device is disclosed and comprises following steps. Firstly, a bottom electrode is formed over a substrate. Next, an oxidation process is performed to the bottom electrode to form a metal oxide layer, wherein a hydrogen plasma and an oxygen plasma are provided during the oxidation process. Then, a top electrode is formed on the metal oxide layer.

    Abstract translation: 公开了一种制造电阻式存储器件的方法，包括以下步骤。 首先，在基板上形成底部电极。 接下来，对底部电极进行氧化处理以形成金属氧化物层，其中在氧化过程中提供氢等离子体和氧等离子体。 然后，在金属氧化物层上形成顶部电极。

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