-
公开(公告)号：US12057162B2
公开(公告)日：2024-08-06
申请号：US17929318
申请日：2022-09-02
发明人： Yu-Yu Lin , Feng-Min Lee
CPC分类号： G11C13/0002 , H03K19/20
摘要： An in-memory-computing method for a memory device includes: storing weight values in cascaded computing cells each including first and second computing memory cells, wherein the first computing memory cells are cascaded in series into a first computing memory cell string and the second computing memory cells are cascaded in series into a second computing memory cell string: receiving input values by the first and the second computing memory cell strings; performing a first logic operation on the input values and the weight values by the first computing memory cell string to generate a first logic operation result, and performing a second logic operation on the input values and the weight values by the second computing memory cell string to generate a second logic operation result: and performing a third logic operation on the first and the second logic operation results to generate an output logic operation result.
-
公开(公告)号：US11847021B2
公开(公告)日：2023-12-19
申请号：US17680388
申请日：2022-02-25
发明人： Yu-Yu Lin , Feng-Min Lee
CPC分类号： G06F11/1004 , G06F3/064 , G06F3/0619 , G06F3/0673
摘要： An operation method of memory device, comprising: selecting a target block for performing an error correction operation; reading the target block row by row; transmitting the read data to an error correction circuit; and checking and correcting read data to generate a corrected data.
-
公开(公告)号：US10719296B2
公开(公告)日：2020-07-21
申请号：US15873369
申请日：2018-01-17
发明人： Feng-Min Lee , Yu-Yu Lin
IPC分类号： G06F7/544 , H03K19/17704 , G11C16/04 , G11C11/54 , H01L27/1157 , H01L27/11524 , H01L45/00
摘要： A device for generating sum-of-products data includes an array of variable resistance cells, variable resistance cells in the array each comprising a programmable threshold transistor and a resistor connected in parallel, the array including n columns of cells including strings of series-connected cells and m rows of cells. Control and bias circuitry are coupled to the array, including logic for programming the programmable threshold transistors in the array with thresholds corresponding to values of a weight factor Wmn for the corresponding cell. Input drivers are coupled to corresponding ones of the m rows of cells, the input drivers selectively applying inputs Xm to rows m. Column drivers are configured to apply currents In to corresponding ones of the n columns of cells. Voltage sensing circuits operatively coupled to the columns of cells.
-
4.发明授权公开(公告)号：US10482953B1
公开(公告)日：2019-11-19
申请号：US16103022
申请日：2018-08-14
发明人： Yu-Hsuan Lin , Yu-Yu Lin , Feng-Min Lee , Chao-Hung Wang , Po-Hao Tseng , Kai-Chieh Hsu
摘要： A multi-state memory device includes a first memory element, a second memory element, a first controlling element and a second controlling element. The second memory element has a memory cell structure identical to that of the first memory element and connects to the first memory element in series. The first controlling element is connected to the first memory element either in series or in parallel. The second controlling element has a characteristic value identical to that of the first controlling element and is connected to the second memory element by a connection structure identical to that of the first controlling element. When the first memory element receives a first signal and a second signal through the first controlling element, a first state value and a second state value are generated correspondingly, and the characteristic value is greater than the first state value and less than the second state value.
-
公开(公告)号：US20190067574A1
公开(公告)日：2019-02-28
申请号：US15690353
申请日：2017-08-30
发明人： Yu-Yu Lin , Feng-Min Lee , Po-Hao Tseng , Kai-Chieh Hsu
CPC分类号： H01L45/1641 , G11C13/0007 , G11C13/0069 , G11C13/0097 , G11C2013/0083 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/147 , H05K3/3494
摘要： A method for treating a semiconductor structure is provided. A semiconductor structure comprising memory devices is provided. A forming process is conducted to initialize operation of the memory devices. The semiconductor structure is subjected to a forming thermal treatment, and step of saving data to the memory devices is performed after the forming thermal treatment.
-
公开(公告)号：US09959928B1
公开(公告)日：2018-05-01
申请号：US15377071
申请日：2016-12-13
发明人： Kai-Chieh Hsu , Feng-Min Lee , Yu-Yu Lin
CPC分类号： G11C13/0064 , G11C13/0007 , G11C13/0069 , G11C2013/0085 , G11C2013/0088 , G11C2013/0092 , G11C2213/79
摘要： A method to program a programmable resistance memory cell includes performing one or more iterations until a verifying passes. The iterations include a) applying a programming pulse to the memory cell, and, b) after applying the programming pulse, verifying if the resistance of the memory cell is in a target resistance range. After an iteration of the one or more iterations in which the verifying passes, c) a stabilizing pulse with a polarity the same as the programming pulse is applied to the memory cell. After applying the stabilizing pulse, a second verifying determines if the resistance of the programmable element is in the target resistance range. Iterations comprising steps a), b), c), and d) are performed until the second verifying passes. Methods and apparatus are described to program a plurality of such cells, including applying a stabilizing pulse of the same polarity after programming.
-
7.发明申请公开(公告)号：US20170179384A1
公开(公告)日：2017-06-22
申请号：US14977770
申请日：2015-12-22
发明人： Feng-Min Lee , Yu-Yu Lin
IPC分类号： H01L45/00
CPC分类号： H01L45/1233 , H01L45/04 , H01L45/146 , H01L45/1608 , H01L45/1633
摘要： A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises a lower electrode, an upper insulating layer, a material layer, a dielectric film, and an upper electrode. The upper insulating layer is on the lower electrode. The material layer is on the upper insulating layer. The upper insulating layer and the material layer have a common opening to expose a portion of the lower electrode. The dielectric film is on the exposed portion of the lower electrode. The dielectric film and the material layer contain a same first transition metal. The upper electrode is on the dielectric film and fills the common opening.
-
公开(公告)号：US20170047514A1
公开(公告)日：2017-02-16
申请号：US14825209
申请日：2015-08-13
发明人： Yu-Yu Lin , Feng-Min Lee
IPC分类号： H01L45/00
CPC分类号： H01L45/1633 , H01L45/08 , H01L45/1233 , H01L45/146
摘要： A method for manufacturing a resistive memory device is disclosed and comprises following steps. Firstly, a bottom electrode is formed over a substrate. Next, an oxidation process is performed to the bottom electrode to form a metal oxide layer, wherein a hydrogen plasma and an oxygen plasma are provided during the oxidation process. Then, a top electrode is formed on the metal oxide layer.
摘要翻译： 公开了一种制造电阻式存储器件的方法，包括以下步骤。 首先，在基板上形成底部电极。 接下来，对底部电极进行氧化处理以形成金属氧化物层，其中在氧化过程中提供氢等离子体和氧等离子体。 然后，在金属氧化物层上形成顶部电极。
-
9.发明申请公开(公告)号：US20150357562A1
公开(公告)日：2015-12-10
申请号：US14297689
申请日：2014-06-06
发明人： Yu-Yu Lin , Feng-Min Lee , Ming-Hsiu Lee
IPC分类号： H01L45/00
CPC分类号： H01L45/1233 , G11C13/0007 , H01L45/04 , H01L45/08 , H01L45/145 , H01L45/146 , H01L45/1633
摘要： A semiconductor structure, a resistive random access memory unit structure, and a manufacturing method of the semiconductor structure are provided. The semiconductor structure includes an insulating structure, a stop layer, a metal oxide layer, a resistance structure, and an electrode material layer. The insulating structure has a via, and the stop layer is formed in the via. The metal oxide layer is formed on the stop layer. The resistance structure is formed at a bottom of an outer wall of the metal oxide layer. The electrode material layer is formed on the metal oxide layer.
摘要翻译： 提供半导体结构，电阻随机存取存储器单元结构以及半导体结构的制造方法。 半导体结构包括绝缘结构，停止层，金属氧化物层，电阻结构和电极材料层。 绝缘结构具有通孔，并且阻挡层形成在通路中。 在停止层上形成金属氧化物层。 电阻结构形成在金属氧化物层的外壁的底部。 在金属氧化物层上形成电极材料层。
-
公开(公告)号：US20150138871A1
公开(公告)日：2015-05-21
申请号：US14085839
申请日：2013-11-21
发明人： Ming-Hsiu Lee , Feng-Min Lee , Yu-Yu Lin
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/0097 , G11C2013/0073 , G11C2013/0078 , G11C2213/79
摘要： Provided is an operation method applicable to a resistive memory cell including a transistor and a resistive memory element. The operation method includes: in a programming operation, generating a programming current flowing through the transistor and the resistive memory element so that a resistance state of the resistive memory element changes from a first resistance state into a second resistance state; and in an erase operation, generating an erase current from a well region of the transistor to the resistive memory element but keeping the erase current from flowing through the transistor, so that the resistance state of the resistive memory element changes from the second resistance state into the first resistance state.
摘要翻译： 提供了一种适用于包括晶体管和电阻性存储元件的电阻式存储单元的操作方法。 操作方法包括：在编程操作中，产生流过晶体管和电阻存储元件的编程电流，使得电阻性存储元件的电阻状态从第一电阻状态变为第二电阻状态; 并且在擦除操作中，产生从晶体管的阱区到电阻存储元件的擦除电流，但是保持擦除电流不流过晶体管，使得电阻性存储元件的电阻状态从第二电阻状态变为 第一个阻力状态。
-
-
-
-
-
-
-
-
-
搜索结果
51 条记录 (耗时 0.024 秒)
