公开(公告)号：US09252156B2

公开(公告)日：2016-02-02

申请号：US14633040

申请日：2015-02-26

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Hao Shih ,  Yi-Hsuan Hsiao ,  Chih-Ping Chen

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11575

Abstract: A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.

公开(公告)号：US08987914B2

公开(公告)日：2015-03-24

申请号：US13907607

申请日：2013-05-31

Applicant: Macronix International Co., Ltd.

Inventor： Yen-Hao Shih ,  Yi-Hsuan Hsiao ,  Chih-Ping Chen

IPC: H01L23/498 ,  H01L21/768 ,  H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11575

Abstract: A method of forming an interlayer conductor structure. The method includes forming a stack of semiconductor pads coupled to respective active layers for a circuit. The semiconductor pads include outside perimeters each having one side coupled to a respective active layer. Impurities are implanted along the outside perimeters to form outside lower resistance regions on the pads. Openings are then formed in the stack of the semiconductor pads to expose a landing area for interlayer conductors on a corresponding semiconductor pad and to define an inside perimeter on at least one of the semiconductor pads. Inside lower resistance regions are formed along the inside perimeters by implanting impurities for interlayer conductor contacts and configured to overlap and be continuous with the corresponding outside lower resistance region.

Abstract translation: 一种形成层间导体结构的方法。 该方法包括形成耦合到用于电路的相应有源层的半导体焊盘堆叠。 半导体焊盘包括外周边，每个外围具有耦合到相应有源层的一侧。 杂质沿着外部周边植入，以形成垫上的较低电阻区域外部。 然后在半导体焊盘的堆叠中形成开口，以暴露对应的半导体焊盘上的层间导体的着陆区域，并且在至少一个半导体焊盘上限定内部周边。 通过注入用于层间导体接触的杂质并且被配置为与相应的外部较低电阻区域重叠并连续地沿着内周边形成内部较低电阻区域。

公开(公告)号：US09419010B2

公开(公告)日：2016-08-16

申请号：US14488937

申请日：2014-09-17

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yen-Hao Shih ,  Chih-Ping Chen ,  Sheng-Chih Lai

IPC: H01L27/115 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/768 ,  H01L27/11556

Abstract: A plurality of semiconductor layers is etched to define a first plurality of stacks of active strips between a first plurality of trenches. A first memory layer is formed on side surfaces of active strips in the first plurality of trenches, and a first layer of conductive material is formed over the first memory layer. The first plurality of stacks is etched to define a second plurality of stacks of active strips between a second plurality of trenches of the plurality of semiconductor layers. A second memory layer is formed on side surfaces of active strips in the second plurality of trenches, and a second layer of conductive material is formed over the second memory layer. Channel regions of memory cells in the memory device are formed in active strips of the plurality of semiconductor layers in the second plurality of stacks.

Abstract translation: 蚀刻多个半导体层以在第一多个沟槽之间限定活动条的第一多个堆叠。 第一存储层形成在第一多个沟槽中的活性条的侧表面上，并且第一层导电材料形成在第一存储层上。 蚀刻第一组多个叠层以在多个半导体层的第二多个沟槽之间限定有效条带的第二多个叠层。 第二存储层形成在第二多个沟槽中的活性条的侧表面上，并且第二层导电材料形成在第二存储层上。 存储器件中的存储器单元的通道区域形成在第二多个堆叠中的多个半导体层的有源条带中。