公开(公告)号：US20160103763A1

公开(公告)日：2016-04-14

申请号：US14513899

申请日：2014-10-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chung-Hsiung Hung

IPC: G06F12/06

CPC classification number: G11C16/10 ,  G11C7/1084 ,  G11C11/5628 ,  G11C16/24 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5621

Abstract: One aspect of the technology is a memory device, which comprises a plurality of page buffers and control circuitry. Different page buffer circuits in the plurality of page buffer circuits are coupled to different bit lines in a plurality of bit lines in a memory array. The control circuitry is responsive to a program command to program multiple cells in the memory array, by setting, via the plurality of page buffer circuits, different target voltages at a same time for the different bit lines coupled to the multiple cells.

Abstract translation: 该技术的一个方面是存储器件，其包括多个页缓冲器和控制电路。 多个页缓冲器电路中的不同页缓冲器电路被耦合到存储器阵列中的多个位线中的不同位线。 控制电路响应于程序命令来对存储器阵列中的多个单元进行编程，通过多个页缓冲器电路同时针对耦合到多个单元的不同位线同时设置不同的目标电压。

公开(公告)号：US09887009B2

公开(公告)日：2018-02-06

申请号：US14513899

申请日：2014-10-14

Applicant: Macronix International Co., Ltd.

Inventor： Chung-Kuang Chen ,  Han-Sung Chen ,  Chung-Hsiung Hung

IPC: G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  G11C7/10 ,  G11C11/56 ,  G11C16/32

CPC classification number: G11C16/10 ,  G11C7/1084 ,  G11C11/5628 ,  G11C16/24 ,  G11C16/32 ,  G11C16/3459 ,  G11C2211/5621

Abstract: One aspect of the technology is a memory device, which comprises a plurality of page buffers and control circuitry. Different page buffer circuits in the plurality of page buffer circuits are coupled to different bit lines in a plurality of bit lines in a memory array. The control circuitry is responsive to a program command to program multiple cells in the memory array, by setting, via the plurality of page buffer circuits, different target voltages at a same time for the different bit lines coupled to the multiple cells.